This commit is contained in:
wangfiox 2024-07-26 23:22:00 +08:00
parent a17a3c7314
commit 962c4b8853
2 changed files with 57 additions and 4 deletions

View File

@ -10,10 +10,9 @@
flake-utils.lib.eachDefaultSystem (system:
let
pkgs = import nixpkgs { inherit system; };
overrides = builtins.fromTOML (builtins.readFile ./rust-toolchain.toml);
libPath = pkgs.lib.makeLibraryPath [
# load external libraries that you need in your rust project here
"./sysy-data/"
"."
];
in {
devShell = pkgs.mkShell {
@ -34,8 +33,6 @@
LD_LIBRARY_PATH = libPath;
RUSTC_VERSION = overrides.toolchain.channel;
shellHook = ''
export PATH=$PATH:''${CARGO_HOME:-~/.cargo}/bin
export PATH=$PATH:''${RUSTUP_HOME:-~/.rustup}/toolchains/$RUSTC_VERSION-x86_64-unknown-linux-gnu/bin/

56
zci.toml Normal file
View File

@ -0,0 +1,56 @@
data_dir = "."
cases = ["functional_c"]
server = "http://10.249.12.73/zci"
executer = "simulate_1"
[test]
task_name = "test"
task_path = "./data_cli/task1"
cases = ["performance_c"]
server_ip = "10.249.12.73"
server_port = 8080
tag = "starfive"
[test.config]
cache = false
execute_cmd = "{bin}"
total_timeout = 10000
case_timeout = 1000
per_timeout = 100
intermediary_break = false
# [test.config.envs]
# LD_LIBRARY_PATH = "$LD_LIBRARY_PATH:data/lib"
[status]
server_ip = "10.249.12.73"
server_port = 8080
[compile]
cache = false
# compiler = "clang"
compiler = "/home/wangfiox/Documents/compiler/target/debug/compiler-cs"
# compile_cmd = "{compiler} -S {sy} -l {asm} -o /dev/null"
compile_cmd = "{compiler} -S {sy} -o {asm}"
[asm2bin]
cache = false
asm2bin_cmd = "riscv64-unknown-linux-gnu-gcc {asm} -Llib -lsysy -march=rv64gc -o {bin}"
[execute]
cache = false
execute_cmd = "qemu-riscv64 {bin}"
per_timeout = 20
intermediary_break = false
[expect]
cache = false
compile_cmd = "riscv64-unknown-linux-gnu-gcc -x c {sy} -S -o {asm} -march=rv64gc"
asm2bin_cmd = "riscv64-unknown-linux-gnu-gcc {asm} -Lsysy-data/lib -lsysy -march=rv64gc -o {bin}"
execute_cmd = "qemu-riscv64 {bin}"
[clean]
dirs = ["asm", "bin", "diff", "output", "log"] # "expect",
[diff]
cache = true
diff_cmd = "diff {out1} {out2}"