diff --git a/Cargo.lock b/Cargo.lock index c572d82..3b11cf0 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2,15 +2,6 @@ # It is not intended for manual editing. version = 3 -[[package]] -name = "aho-corasick" -version = "1.1.3" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916" -dependencies = [ - "memchr", -] - [[package]] name = "atty" version = "0.2.14" @@ -47,12 +38,6 @@ version = "2.5.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1" -[[package]] -name = "cc" -version = "1.0.99" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "96c51067fd44124faa7f870b4b1c969379ad32b2ba805aa959430ceaa384f695" - [[package]] name = "cfg-if" version = "1.0.0" @@ -174,7 +159,6 @@ version = "0.1.0" dependencies = [ "clap", "lazy_static", - "llvm-ir", "once_cell", "rand", "rayon", @@ -230,36 +214,6 @@ version = "0.4.14" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89" -[[package]] -name = "llvm-ir" -version = "0.10.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "434db35c1dc3bce4d16bb60c4f6a57587dfa8224ba92fc080fde38782c35fc90" -dependencies = [ - "either", - "llvm-sys", - "log", -] - -[[package]] -name = "llvm-sys" -version = "160.1.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "49f9888529887dfda6c59e20f0e0727b17e826cd54ae1ddf0d4c83850fa23b69" -dependencies = [ - "cc", - "lazy_static", - "libc", - "regex", - "semver", -] - -[[package]] -name = "log" -version = "0.4.21" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c" - [[package]] name = "memchr" version = "2.7.2" @@ -352,35 +306,6 @@ dependencies = [ "crossbeam-utils", ] -[[package]] -name = "regex" -version = "1.10.5" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "b91213439dad192326a0d7c6ee3955910425f441d7038e0d6933b0aec5c4517f" -dependencies = [ - "aho-corasick", - "memchr", - "regex-automata", - "regex-syntax", -] - -[[package]] -name = "regex-automata" -version = "0.4.7" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df" -dependencies = [ - "aho-corasick", - "memchr", - "regex-syntax", -] - -[[package]] -name = "regex-syntax" -version = "0.8.4" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b" - [[package]] name = "rustix" version = "0.38.34" @@ -400,12 +325,6 @@ version = "1.0.18" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f3cb5ba0dc43242ce17de99c180e96db90b235b8a9fdc9543c96d2209116bd9f" -[[package]] -name = "semver" -version = "1.0.23" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b" - [[package]] name = "serde" version = "1.0.203" diff --git a/hitc b/hitc index f3b9eef..c5a2f47 160000 --- a/hitc +++ b/hitc @@ -1 +1 @@ -Subproject commit f3b9eefa3cb53f181d09328a66efeb3343ea7d3f +Subproject commit c5a2f47e6a5817b47ac5670a8c22acc76b0662b4 diff --git a/src/ch2/quicksort.rs b/src/ch2/quicksort.rs index a1c442f..275b21b 100644 --- a/src/ch2/quicksort.rs +++ b/src/ch2/quicksort.rs @@ -1,7 +1,7 @@ // #[cfg(test)] pub mod tests { - use compiler::{backend::*, middle::ir::instruction::binary_inst::Add}; - use var::{ArrVar, Str, Var}; + use compiler::backend::*; + use var::*; #[test] pub fn quicksort_example() { @@ -11,20 +11,10 @@ pub mod tests { let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into())); let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into())); let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into())); - let bgea1a2lbb0_17 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_A1.into(), - REG_A2.into(), - "LBB0_17".into(), - )); - entry.extend_insts(vec![ - addispsp_32, - sdra24sp, - sds016sp, - sds18sp, - sds20sp, - bgea1a2lbb0_17, - ]); + let bgea1a2lbb0_17 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into()) + ); + entry.extend_insts(vec![addispsp_32, sdra24sp, sds016sp, sds18sp, sds20sp, bgea1a2lbb0_17]); let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into())); let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into())); let jlbb0_3 = Inst::Jmp(JmpInst::new("LBB0_3".into())); @@ -38,34 +28,30 @@ pub mod tests { let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into())); let callquicksort = Inst::Call(CallInst::new("QuickSort".into())); let addia1s01 = Inst::Add(AddInst::new(REG_A1.into(), REG_S0.into(), (1).into())); - let bgea1s2lbb0_17 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_A1.into(), - REG_S2.into(), - "LBB0_17".into(), - )); - lbb0_2.extend_insts(vec![ - sllia2s02, - adda2a2s1, - swa00a2, - addia2s0_1, - mva0s1, - callquicksort, - addia1s01, - bgea1s2lbb0_17, - ]); + let bgea1s2lbb0_17 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into()) + ); + lbb0_2.extend_insts( + vec![ + sllia2s02, + adda2a2s1, + swa00a2, + addia2s0_1, + mva0s1, + callquicksort, + addia1s01, + bgea1s2lbb0_17 + ] + ); let mut lbb0_3 = Block::new("LBB0_3".into()); let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into())); let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into())); let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into())); let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into())); - let bgea1s2lbb0_2 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_A1.into(), - REG_S2.into(), - "LBB0_2".into(), - )); + let bgea1s2lbb0_2 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into()) + ); lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, lwa00a0, mvs0a1, bgea1s2lbb0_2]); let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into())); let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into())); @@ -80,21 +66,15 @@ pub mod tests { lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, swa40a3, addia2a2_1]); let mut llb0_6 = Block::new("LBB0_6".into()); - let bges0a2lbb0_2 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_S0.into(), - REG_A2.into(), - "LBB0_2".into(), - )); + let bges0a2lbb0_2 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into()) + ); llb0_6.extend_insts(vec![bges0a2lbb0_2]); let mut lbb0_7 = Block::new("LBB0_7".into()); - let bges0a2lbb0_11 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_S0.into(), - REG_A2.into(), - "LBB0_11".into(), - )); + let bges0a2lbb0_11 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into()) + ); lbb0_7.extend_insts(vec![bges0a2lbb0_11]); let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into())); let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into())); @@ -103,31 +83,22 @@ pub mod tests { let mut lbb0_9 = Block::new("LBB0_9".into()); let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into())); - let blta5a0lbb0_12 = Inst::Branch(BranchInst::new( - BranchOp::Blt, - REG_A5.into(), - REG_A0.into(), - "LBB0_12".into(), - )); + let blta5a0lbb0_12 = Inst::Branch( + BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into()) + ); lbb0_9.extend_insts(vec![lwa50a3, blta5a0lbb0_12]); let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into())); let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into())); let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into())); - let blts0a4lbb0_9 = Inst::Branch(BranchInst::new( - BranchOp::Blt, - REG_S0.into(), - REG_A4.into(), - "LBB0_9".into(), - )); + let blts0a4lbb0_9 = Inst::Branch( + BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into()) + ); lbb0_9.extend_insts(vec![addia4a4_1, addia2a2_1, addia3a3_4, blts0a4lbb0_9]); let mut lbb0_11 = Block::new("LBB0_11".into()); - let bges0a2lbb0_6 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_S0.into(), - REG_A2.into(), - "LBB0_6".into(), - )); + let bges0a2lbb0_6 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into()) + ); let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into())); lbb0_11.extend_insts(vec![bges0a2lbb0_6, jlbb0_13]); @@ -136,19 +107,10 @@ pub mod tests { let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into())); let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into())); let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into())); - let bges0a2lbb0_6 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_S0.into(), - REG_A2.into(), - "LBB0_6".into(), - )); - lbb0_12.extend_insts(vec![ - sllia3s02, - adda3a3s1, - swa50a3, - addis0s01, - bges0a2lbb0_6, - ]); + let bges0a2lbb0_6 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into()) + ); + lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, swa50a3, addis0s01, bges0a2lbb0_6]); let mut lbb0_13 = Block::new("LBB0_13".into()); let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into())); @@ -157,22 +119,16 @@ pub mod tests { let mut lbb0_14 = Block::new("LBB0_14".into()); let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into())); - let bgea4a0lbb0_5 = Inst::Branch(BranchInst::new( - BranchOp::Bge, - REG_A4.into(), - REG_A0.into(), - "LBB0_5".into(), - )); + let bgea4a0lbb0_5 = Inst::Branch( + BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into()) + ); lbb0_14.extend_insts(vec![lwa40a3, bgea4a0lbb0_5]); // push_inst lw let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into())); let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into())); - let bnea2s0lbb0_14 = Inst::Branch(BranchInst::new( - BranchOp::Bne, - REG_A2.into(), - REG_S0.into(), - "LBB0_14".into(), - )); + let bnea2s0lbb0_14 = Inst::Branch( + BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into()) + ); lbb0_14.extend_insts(vec![addis0s01, addia3a34, bnea2s0lbb0_14]); let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into())); let jlbb0_2 = Inst::Jmp(JmpInst::new("LBB0_2".into())); @@ -186,9 +142,7 @@ pub mod tests { let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into())); let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into())); let ret = Inst::Ret; - lbb0_17.extend_insts(vec![ - lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret, - ]); + lbb0_17.extend_insts(vec![lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret]); let mut quickSort = Func::new("QuickSort".into(), Vec::new(), entry); quickSort.push_bb(lbb0_2); @@ -220,32 +174,31 @@ pub mod tests { let llas2arr = Inst::La(LaInst::new(REG_S2.into(), "arr+40".into())); // lla s1 LC0 , lc0 is .string "%d\n" let llas1lc0 = Inst::La(LaInst::new(REG_S1.into(), "LC0".into())); - entry.extend_insts(vec![ - addispsp_32, - lia29, - lia10, - /* lla a0, arr */ llaa0arr, - sds016sp, - sds18sp, - sds20sp, - sdra24sp, - llas0arr, - callquicksort, - llas2arr, - llas1lc0, - ]); + entry.extend_insts( + vec![ + addispsp_32, + lia29, + lia10, + /* lla a0, arr */ llaa0arr, + sds016sp, + sds18sp, + sds20sp, + sdra24sp, + llas0arr, + callquicksort, + llas2arr, + llas1lc0 + ] + ); let mut l35 = Block::new("L35".into()); let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into())); let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into())); let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into())); let callprintf = Inst::Call(CallInst::new("printf@plt".into())); - let bnes0s2l35 = Inst::Branch(BranchInst::new( - BranchOp::Bne, - REG_S0.into(), - REG_S2.into(), - "L35".into(), - )); + let bnes0s2l35 = Inst::Branch( + BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into()) + ); let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into())); let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into())); let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into())); @@ -253,10 +206,22 @@ pub mod tests { let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into())); let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into())); let ret = Inst::Ret; - l35.extend_insts(vec![ - lwa10s0, mva0s1, addis0s04, callprintf, bnes0s2l35, ldra24sp, lds016sp, lds18sp, - lds20sp, lia00, addispsp32, ret, - ]); + l35.extend_insts( + vec![ + lwa10s0, + mva0s1, + addis0s04, + callprintf, + bnes0s2l35, + ldra24sp, + lds016sp, + lds18sp, + lds20sp, + lia00, + addispsp32, + ret + ] + ); let mut Main = Func::new("main".into(), Vec::new(), entry); Main.push_bb(l35); @@ -279,7 +244,7 @@ pub mod tests { (6, 6), (7, 5), (8, 7), - (9, 9), + (9, 9) ], is_const: false, }); diff --git a/src/ch3/FuncPoint.rs b/src/ch3/FuncPoint.rs index 3b0e24b..07dcad9 100644 --- a/src/ch3/FuncPoint.rs +++ b/src/ch3/FuncPoint.rs @@ -1,8 +1,5 @@ mod tests { - use compiler::backend::{ - AddInst, Block, BranchInst, BranchOp, Func, Inst, MvInst, SdInst, REG_A0, REG_A1, REG_A5, - REG_RA, REG_S2, REG_S5, REG_SP, REG_ZERO, - }; + use compiler::backend::*; #[test] pub fn test() { @@ -28,12 +25,9 @@ mod tests { /* ---------- ---------- sort ---------- ---------- */ let mut entry = Block::new("entry".into()); let lia51 = Inst::Add(AddInst::new(REG_A5.into(), REG_ZERO.into(), (1).into())); - let blea1a5L20 = Inst::Branch(BranchInst::new( - BranchOp::Ble, - REG_A1.into(), - REG_A5.into(), - "L20".into(), - )); + let blea1a5L20 = Inst::Branch( + BranchInst::new(BranchOp::Ble, REG_A1.into(), REG_A5.into(), "L20".into()) + ); let addispsp_64 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-64).into())); let sds232sp = Inst::Sd(SdInst::new(REG_S2.into(), (32).into(), REG_SP.into())); let sds324sp = Inst::Sd(SdInst::new(REG_S3.into(), (24).into(), REG_SP.into()));