modified: Cargo.lock
modified: hitc modified: src/ch2/quicksort.rs modified: src/ch3/FuncPoint.rs modified: hitc (modified content)
This commit is contained in:
wangfiox
parent
b3ec91ebfd
commit
20f58e176a
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@ -2,15 +2,6 @@
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# It is not intended for manual editing.
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version = 3
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[[package]]
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name = "aho-corasick"
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version = "1.1.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916"
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dependencies = [
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"memchr",
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]
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[[package]]
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name = "atty"
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version = "0.2.14"
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@ -47,12 +38,6 @@ version = "2.5.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
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|
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[[package]]
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name = "cc"
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version = "1.0.99"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "96c51067fd44124faa7f870b4b1c969379ad32b2ba805aa959430ceaa384f695"
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[[package]]
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name = "cfg-if"
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version = "1.0.0"
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@ -174,7 +159,6 @@ version = "0.1.0"
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dependencies = [
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"clap",
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"lazy_static",
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"llvm-ir",
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"once_cell",
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"rand",
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"rayon",
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|
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@ -230,36 +214,6 @@ version = "0.4.14"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89"
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[[package]]
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name = "llvm-ir"
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version = "0.10.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "434db35c1dc3bce4d16bb60c4f6a57587dfa8224ba92fc080fde38782c35fc90"
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dependencies = [
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"either",
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"llvm-sys",
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"log",
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]
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[[package]]
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name = "llvm-sys"
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version = "160.1.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "49f9888529887dfda6c59e20f0e0727b17e826cd54ae1ddf0d4c83850fa23b69"
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dependencies = [
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"cc",
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"lazy_static",
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"libc",
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"regex",
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"semver",
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]
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[[package]]
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name = "log"
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version = "0.4.21"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c"
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[[package]]
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name = "memchr"
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version = "2.7.2"
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@ -352,35 +306,6 @@ dependencies = [
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"crossbeam-utils",
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]
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[[package]]
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name = "regex"
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version = "1.10.5"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b91213439dad192326a0d7c6ee3955910425f441d7038e0d6933b0aec5c4517f"
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dependencies = [
|
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"aho-corasick",
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"memchr",
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"regex-automata",
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"regex-syntax",
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]
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[[package]]
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name = "regex-automata"
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version = "0.4.7"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df"
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dependencies = [
|
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"aho-corasick",
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"memchr",
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"regex-syntax",
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]
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[[package]]
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name = "regex-syntax"
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version = "0.8.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b"
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[[package]]
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name = "rustix"
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version = "0.38.34"
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@ -400,12 +325,6 @@ version = "1.0.18"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "f3cb5ba0dc43242ce17de99c180e96db90b235b8a9fdc9543c96d2209116bd9f"
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|
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[[package]]
|
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name = "semver"
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version = "1.0.23"
|
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b"
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[[package]]
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name = "serde"
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version = "1.0.203"
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|
|
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2
hitc
2
hitc
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@ -1 +1 @@
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Subproject commit f3b9eefa3cb53f181d09328a66efeb3343ea7d3f
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Subproject commit c5a2f47e6a5817b47ac5670a8c22acc76b0662b4
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@ -1,7 +1,7 @@
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// #[cfg(test)]
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pub mod tests {
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use compiler::{backend::*, middle::ir::instruction::binary_inst::Add};
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use var::{ArrVar, Str, Var};
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use compiler::backend::*;
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use var::*;
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#[test]
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pub fn quicksort_example() {
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@ -11,20 +11,10 @@ pub mod tests {
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let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
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let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
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let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
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let bgea1a2lbb0_17 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_A1.into(),
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REG_A2.into(),
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"LBB0_17".into(),
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));
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entry.extend_insts(vec![
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addispsp_32,
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sdra24sp,
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sds016sp,
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sds18sp,
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sds20sp,
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bgea1a2lbb0_17,
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]);
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let bgea1a2lbb0_17 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
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);
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entry.extend_insts(vec![addispsp_32, sdra24sp, sds016sp, sds18sp, sds20sp, bgea1a2lbb0_17]);
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let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
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let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
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let jlbb0_3 = Inst::Jmp(JmpInst::new("LBB0_3".into()));
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@ -38,13 +28,11 @@ pub mod tests {
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let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
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let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
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let addia1s01 = Inst::Add(AddInst::new(REG_A1.into(), REG_S0.into(), (1).into()));
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let bgea1s2lbb0_17 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_A1.into(),
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REG_S2.into(),
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"LBB0_17".into(),
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));
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lbb0_2.extend_insts(vec![
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let bgea1s2lbb0_17 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into())
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);
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lbb0_2.extend_insts(
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vec![
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sllia2s02,
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adda2a2s1,
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swa00a2,
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@ -52,20 +40,18 @@ pub mod tests {
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mva0s1,
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callquicksort,
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addia1s01,
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bgea1s2lbb0_17,
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]);
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bgea1s2lbb0_17
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]
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);
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let mut lbb0_3 = Block::new("LBB0_3".into());
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let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
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let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into()));
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let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
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let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
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let bgea1s2lbb0_2 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_A1.into(),
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REG_S2.into(),
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"LBB0_2".into(),
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));
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let bgea1s2lbb0_2 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into())
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);
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lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, lwa00a0, mvs0a1, bgea1s2lbb0_2]);
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let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
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let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into()));
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@ -80,21 +66,15 @@ pub mod tests {
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lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, swa40a3, addia2a2_1]);
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let mut llb0_6 = Block::new("LBB0_6".into());
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let bges0a2lbb0_2 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_S0.into(),
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REG_A2.into(),
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"LBB0_2".into(),
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));
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let bges0a2lbb0_2 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into())
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);
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llb0_6.extend_insts(vec![bges0a2lbb0_2]);
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let mut lbb0_7 = Block::new("LBB0_7".into());
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let bges0a2lbb0_11 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_S0.into(),
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REG_A2.into(),
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"LBB0_11".into(),
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));
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let bges0a2lbb0_11 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into())
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);
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lbb0_7.extend_insts(vec![bges0a2lbb0_11]);
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let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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@ -103,31 +83,22 @@ pub mod tests {
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let mut lbb0_9 = Block::new("LBB0_9".into());
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let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let blta5a0lbb0_12 = Inst::Branch(BranchInst::new(
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BranchOp::Blt,
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REG_A5.into(),
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REG_A0.into(),
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"LBB0_12".into(),
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));
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let blta5a0lbb0_12 = Inst::Branch(
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BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into())
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);
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lbb0_9.extend_insts(vec![lwa50a3, blta5a0lbb0_12]);
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let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into()));
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let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
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let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into()));
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let blts0a4lbb0_9 = Inst::Branch(BranchInst::new(
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BranchOp::Blt,
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REG_S0.into(),
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REG_A4.into(),
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"LBB0_9".into(),
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));
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let blts0a4lbb0_9 = Inst::Branch(
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BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into())
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);
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lbb0_9.extend_insts(vec![addia4a4_1, addia2a2_1, addia3a3_4, blts0a4lbb0_9]);
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let mut lbb0_11 = Block::new("LBB0_11".into());
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let bges0a2lbb0_6 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_S0.into(),
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REG_A2.into(),
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"LBB0_6".into(),
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));
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let bges0a2lbb0_6 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
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);
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let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into()));
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lbb0_11.extend_insts(vec![bges0a2lbb0_6, jlbb0_13]);
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@ -136,19 +107,10 @@ pub mod tests {
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
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let bges0a2lbb0_6 = Inst::Branch(BranchInst::new(
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BranchOp::Bge,
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REG_S0.into(),
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REG_A2.into(),
|
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"LBB0_6".into(),
|
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));
|
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lbb0_12.extend_insts(vec![
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sllia3s02,
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adda3a3s1,
|
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swa50a3,
|
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addis0s01,
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bges0a2lbb0_6,
|
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]);
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let bges0a2lbb0_6 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
|
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);
|
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lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, swa50a3, addis0s01, bges0a2lbb0_6]);
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|
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let mut lbb0_13 = Block::new("LBB0_13".into());
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let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
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|
|
@ -157,22 +119,16 @@ pub mod tests {
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let mut lbb0_14 = Block::new("LBB0_14".into());
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let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
|
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let bgea4a0lbb0_5 = Inst::Branch(BranchInst::new(
|
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BranchOp::Bge,
|
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REG_A4.into(),
|
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REG_A0.into(),
|
||||
"LBB0_5".into(),
|
||||
));
|
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let bgea4a0lbb0_5 = Inst::Branch(
|
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BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into())
|
||||
);
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lbb0_14.extend_insts(vec![lwa40a3, bgea4a0lbb0_5]);
|
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// push_inst lw
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let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
|
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let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into()));
|
||||
let bnea2s0lbb0_14 = Inst::Branch(BranchInst::new(
|
||||
BranchOp::Bne,
|
||||
REG_A2.into(),
|
||||
REG_S0.into(),
|
||||
"LBB0_14".into(),
|
||||
));
|
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let bnea2s0lbb0_14 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into())
|
||||
);
|
||||
lbb0_14.extend_insts(vec![addis0s01, addia3a34, bnea2s0lbb0_14]);
|
||||
let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into()));
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let jlbb0_2 = Inst::Jmp(JmpInst::new("LBB0_2".into()));
|
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|
|
@ -186,9 +142,7 @@ pub mod tests {
|
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let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
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let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
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let ret = Inst::Ret;
|
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lbb0_17.extend_insts(vec![
|
||||
lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret,
|
||||
]);
|
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lbb0_17.extend_insts(vec![lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret]);
|
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|
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let mut quickSort = Func::new("QuickSort".into(), Vec::new(), entry);
|
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quickSort.push_bb(lbb0_2);
|
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|
|
@ -220,7 +174,8 @@ pub mod tests {
|
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let llas2arr = Inst::La(LaInst::new(REG_S2.into(), "arr+40".into()));
|
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// lla s1 LC0 , lc0 is .string "%d\n"
|
||||
let llas1lc0 = Inst::La(LaInst::new(REG_S1.into(), "LC0".into()));
|
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entry.extend_insts(vec![
|
||||
entry.extend_insts(
|
||||
vec![
|
||||
addispsp_32,
|
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lia29,
|
||||
lia10,
|
||||
|
|
@ -232,20 +187,18 @@ pub mod tests {
|
|||
llas0arr,
|
||||
callquicksort,
|
||||
llas2arr,
|
||||
llas1lc0,
|
||||
]);
|
||||
llas1lc0
|
||||
]
|
||||
);
|
||||
|
||||
let mut l35 = Block::new("L35".into());
|
||||
let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
|
||||
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
|
||||
let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into()));
|
||||
let callprintf = Inst::Call(CallInst::new("printf@plt".into()));
|
||||
let bnes0s2l35 = Inst::Branch(BranchInst::new(
|
||||
BranchOp::Bne,
|
||||
REG_S0.into(),
|
||||
REG_S2.into(),
|
||||
"L35".into(),
|
||||
));
|
||||
let bnes0s2l35 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into())
|
||||
);
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
|
|
@ -253,10 +206,22 @@ pub mod tests {
|
|||
let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
l35.extend_insts(vec![
|
||||
lwa10s0, mva0s1, addis0s04, callprintf, bnes0s2l35, ldra24sp, lds016sp, lds18sp,
|
||||
lds20sp, lia00, addispsp32, ret,
|
||||
]);
|
||||
l35.extend_insts(
|
||||
vec![
|
||||
lwa10s0,
|
||||
mva0s1,
|
||||
addis0s04,
|
||||
callprintf,
|
||||
bnes0s2l35,
|
||||
ldra24sp,
|
||||
lds016sp,
|
||||
lds18sp,
|
||||
lds20sp,
|
||||
lia00,
|
||||
addispsp32,
|
||||
ret
|
||||
]
|
||||
);
|
||||
let mut Main = Func::new("main".into(), Vec::new(), entry);
|
||||
Main.push_bb(l35);
|
||||
|
||||
|
|
@ -279,7 +244,7 @@ pub mod tests {
|
|||
(6, 6),
|
||||
(7, 5),
|
||||
(8, 7),
|
||||
(9, 9),
|
||||
(9, 9)
|
||||
],
|
||||
is_const: false,
|
||||
});
|
||||
|
|
|
|||
|
|
@ -1,8 +1,5 @@
|
|||
mod tests {
|
||||
use compiler::backend::{
|
||||
AddInst, Block, BranchInst, BranchOp, Func, Inst, MvInst, SdInst, REG_A0, REG_A1, REG_A5,
|
||||
REG_RA, REG_S2, REG_S5, REG_SP, REG_ZERO,
|
||||
};
|
||||
use compiler::backend::*;
|
||||
|
||||
#[test]
|
||||
pub fn test() {
|
||||
|
|
@ -28,12 +25,9 @@ mod tests {
|
|||
/* ---------- ---------- sort ---------- ---------- */
|
||||
let mut entry = Block::new("entry".into());
|
||||
let lia51 = Inst::Add(AddInst::new(REG_A5.into(), REG_ZERO.into(), (1).into()));
|
||||
let blea1a5L20 = Inst::Branch(BranchInst::new(
|
||||
BranchOp::Ble,
|
||||
REG_A1.into(),
|
||||
REG_A5.into(),
|
||||
"L20".into(),
|
||||
));
|
||||
let blea1a5L20 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Ble, REG_A1.into(), REG_A5.into(), "L20".into())
|
||||
);
|
||||
let addispsp_64 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-64).into()));
|
||||
let sds232sp = Inst::Sd(SdInst::new(REG_S2.into(), (32).into(), REG_SP.into()));
|
||||
let sds324sp = Inst::Sd(SdInst::new(REG_S3.into(), (24).into(), REG_SP.into()));
|
||||
|
|
|
|||
Loading…
Reference in New Issue