modified: src/ch2/linkedlist.rs
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0dd21eca39
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3cb60c9922
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@ -241,15 +241,34 @@ pub mod tests {
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sdzero8a0,
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]);
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//.L11:
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// mv a4,a5
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// ld a5,8(a5)
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// bne a5,zero,.L11
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// ld ra,24(sp)
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// ld s0,16(sp)
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// sd a0,8(a4)
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// ld s1,8(sp)
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// addi sp,sp,32
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// jr ra
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let mut l11 = Block::new("L11".into());
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let mva4a5 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A5.into()));
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let lda58a5 = Inst::Ld(LdInst::new(REG_A5.into(), (8).into(), REG_A5.into()));
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let bnea5zeroL11 = Inst::Branch(BranchInst::new(
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BranchOp::Bne,
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REG_A5.into(),
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REG_ZERO.into(),
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"L11".into(),
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));
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let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
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let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
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let sds08sp = Inst::Sd(SdInst::new(REG_S0.into(), (8).into(), REG_A4.into()));
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let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
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let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
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let ret = Inst::Ret;
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l11.extend_insts(vec![
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mva4a5,
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lda58a5,
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bnea5zeroL11,
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ldra24sp,
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lds016sp,
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sds08sp,
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lds18sp,
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addispsp32,
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ret,
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]);
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let mut insertNode = Func::new("insertNode".into(), Vec::new(), entry);
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insertNode.push_bb(l11);
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}
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}
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