diff --git a/Cargo.lock b/Cargo.lock
index 3b11cf0..c572d82 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -2,6 +2,15 @@
 # It is not intended for manual editing.
 version = 3
 
+[[package]]
+name = "aho-corasick"
+version = "1.1.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916"
+dependencies = [
+ "memchr",
+]
+
 [[package]]
 name = "atty"
 version = "0.2.14"
@@ -38,6 +47,12 @@ version = "2.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
 
+[[package]]
+name = "cc"
+version = "1.0.99"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "96c51067fd44124faa7f870b4b1c969379ad32b2ba805aa959430ceaa384f695"
+
 [[package]]
 name = "cfg-if"
 version = "1.0.0"
@@ -159,6 +174,7 @@ version = "0.1.0"
 dependencies = [
  "clap",
  "lazy_static",
+ "llvm-ir",
  "once_cell",
  "rand",
  "rayon",
@@ -214,6 +230,36 @@ version = "0.4.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89"
 
+[[package]]
+name = "llvm-ir"
+version = "0.10.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "434db35c1dc3bce4d16bb60c4f6a57587dfa8224ba92fc080fde38782c35fc90"
+dependencies = [
+ "either",
+ "llvm-sys",
+ "log",
+]
+
+[[package]]
+name = "llvm-sys"
+version = "160.1.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "49f9888529887dfda6c59e20f0e0727b17e826cd54ae1ddf0d4c83850fa23b69"
+dependencies = [
+ "cc",
+ "lazy_static",
+ "libc",
+ "regex",
+ "semver",
+]
+
+[[package]]
+name = "log"
+version = "0.4.21"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c"
+
 [[package]]
 name = "memchr"
 version = "2.7.2"
@@ -306,6 +352,35 @@ dependencies = [
  "crossbeam-utils",
 ]
 
+[[package]]
+name = "regex"
+version = "1.10.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b91213439dad192326a0d7c6ee3955910425f441d7038e0d6933b0aec5c4517f"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-automata",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-automata"
+version = "0.4.7"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df"
+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
+]
+
+[[package]]
+name = "regex-syntax"
+version = "0.8.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b"
+
 [[package]]
 name = "rustix"
 version = "0.38.34"
@@ -325,6 +400,12 @@ version = "1.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f3cb5ba0dc43242ce17de99c180e96db90b235b8a9fdc9543c96d2209116bd9f"
 
+[[package]]
+name = "semver"
+version = "1.0.23"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b"
+
 [[package]]
 name = "serde"
 version = "1.0.203"
diff --git a/Cargo.toml b/Cargo.toml
index 49dde6a..a7068f2 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -5,3 +5,6 @@ edition = "2021"
 
 [dependencies]
 hitc = { path = "/home/wangfiox/Documents/compiler" }
+
+#[features]
+#default = ["test"]
diff --git a/src/ch2/mod.rs b/src/ch2/mod.rs
index 12c030d..7c5c655 100644
--- a/src/ch2/mod.rs
+++ b/src/ch2/mod.rs
@@ -1,3 +1,3 @@
-mod sizeof;
+mod quicksort;
 
-pub use sizeof::*;
+pub use quicksort::*;
diff --git a/src/ch2/quicksort.rs b/src/ch2/quicksort.rs
new file mode 100644
index 0000000..309792e
--- /dev/null
+++ b/src/ch2/quicksort.rs
@@ -0,0 +1,179 @@
+//#[cfg(test)]
+pub mod tests {
+    use compiler::backend::*;
+
+    #[test]
+    pub fn quicksort() {
+        let quickSort = Func::new("QuickSort".into(), Vec::new());
+
+        let mut bb0 = Block::new("bb0".into());
+        let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
+        let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
+        let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
+        let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
+        let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
+        let bgea1a2lbb0_17 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
+        );
+        bb0.push_inst(addispsp_32);
+        bb0.push_inst(sdra24sp);
+        bb0.push_inst(sds016sp);
+        bb0.push_inst(sds18sp);
+        bb0.push_inst(sds20sp);
+        bb0.push_inst(bgea1a2lbb0_17);
+
+        let mut bb1 = Block::new("bb1".into());
+        let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
+        let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
+        let jlbb0_3 = Inst::Jmp(JmpInst::new("LBB0_3".into()));
+        bb1.push_inst(mvs2a2);
+        bb1.push_inst(mvs1a0);
+        bb1.push_inst(jlbb0_3);
+
+        let mut lbb0_2 = Block::new("lbb0_2".into());
+        let sllia2s02 = Inst::SLL(SllInst::new(REG_A2.into(), REG_S0.into(), (2).into()));
+        let adda2a2s1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), REG_S1.into()));
+        let swa00a2 = Inst::Sd(SdInst::new(REG_A0.into(), (0).into(), REG_A2.into()));
+        let addia2s0_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_S0.into(), (-1).into()));
+        let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
+        let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
+        let addia1s01 = Inst::Add(AddInst::new(REG_A1.into(), REG_S0.into(), (1).into()));
+        let bgea1s2lbb0_17 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into())
+        );
+        lbb0_2.push_inst(sllia2s02);
+        lbb0_2.push_inst(adda2a2s1);
+        lbb0_2.push_inst(swa00a2);
+        lbb0_2.push_inst(addia2s0_1);
+        lbb0_2.push_inst(mva0s1);
+        lbb0_2.push_inst(callquicksort);
+        lbb0_2.push_inst(addia1s01);
+        lbb0_2.push_inst(bgea1s2lbb0_17);
+
+        let mut lbb0_3 = Block::new("LBB0_3".into());
+        let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
+        let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into()));
+        // let lwa00a0 = Inst::
+        let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
+        let bgea1s2lbb0_2 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into())
+        );
+        lbb0_3.push_inst(sllia0a12);
+        lbb0_3.push_inst(adda0a0s1);
+        // lbb0_3.push_inst(lwa00a0)
+        lbb0_3.push_inst(mvs0a1);
+        lbb0_3.push_inst(bgea1s2lbb0_2);
+
+        let mut bb4 = Block::new("bb4".into());
+        let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
+        let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into()));
+        let jlbb0_7 = Inst::Jmp(JmpInst::new("LBB0_7".into()));
+        bb4.push_inst(mvs0a1);
+        bb4.push_inst(mva2s2);
+        bb4.push_inst(jlbb0_7);
+
+        let mut lbb0_5 = Block::new("LBB0_5".into());
+        let sllis3s22 = Inst::SLL(SllInst::new(REG_S3.into(), REG_S2.into(), (2).into()));
+        let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
+        let swa40a3 = Inst::Sd(SdInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
+        let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
+        lbb0_5.push_inst(sllis3s22);
+        lbb0_5.push_inst(adda3a3s1);
+        lbb0_5.push_inst(swa40a3);
+        lbb0_5.push_inst(addia2a2_1);
+
+        let mut llb0_6 = Block::new("LBB0_6".into());
+        let bges0a2lbb0_2 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into())
+        );
+        llb0_6.push_inst(bges0a2lbb0_2);
+
+        let mut lbb0_7 = Block::new("LBB0_7".into());
+        let bges0a2lbb0_11 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into())
+        );
+        lbb0_7.push_inst(bges0a2lbb0_11);
+
+        let mut bb8 = Block::new("bb8".into());
+        let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
+        let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
+        let mva4a2 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A2.into()));
+        bb8.push_inst(sllia3a22);
+        bb8.push_inst(adda3a3s1);
+        bb8.push_inst(mva4a2);
+
+        let mut lbb0_9 = Block::new("LBB0_9".into());
+        let lwa50a3 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
+        let blta5a0lbb0_12 = Inst::Branch(
+            BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into())
+        );
+        lbb0_9.push_inst(lwa50a3);
+        lbb0_9.push_inst(blta5a0lbb0_12);
+
+        let mut bb10 = Block::new("bb10".into());
+        let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into()));
+        let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
+        let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into()));
+        let blts0a4lbb0_9 = Inst::Branch(
+            BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into())
+        );
+        bb10.push_inst(addia4a4_1);
+        bb10.push_inst(addia2a2_1);
+        bb10.push_inst(addia3a3_4);
+
+        let mut lbb0_11 = Block::new("LBB0_11".into());
+        let bges0a2lbb0_6 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
+        );
+        let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into()));
+        lbb0_11.push_inst(bges0a2lbb0_6);
+        lbb0_11.push_inst(jlbb0_13);
+
+        let mut lbb0_12 = Block::new("LBB0_12".into());
+        let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
+        let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
+        let swa50a3 = Inst::Sd(SdInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
+        let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
+        let bges0a2lbb0_6 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
+        );
+        lbb0_12.push_inst(sllia3s02);
+        lbb0_12.push_inst(adda3a3s1);
+        lbb0_12.push_inst(swa50a3);
+        lbb0_12.push_inst(addis0s01);
+        lbb0_12.push_inst(bges0a2lbb0_6);
+
+        let mut lbb0_13 = Block::new("LBB0_13".into());
+        let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
+        let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
+        lbb0_13.push_inst(sllia3s02);
+        lbb0_13.push_inst(adda3a3s1);
+
+        let mut lbb0_14 = Block::new("LBB0_14".into());
+        // lw a4, 0(a3)
+        let bgea4a0lbb0_5 = Inst::Branch(
+            BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into())
+        );
+        // lw
+        lbb0_14.push_inst(bgea4a0lbb0_5);
+
+        let mut lbb0_15 = Block::new("LBB0_15".into());
+        let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
+        let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into()));
+        let bnea2s0lbb0_14 = Inst::Branch(
+            BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into())
+        );
+        lbb0_15.push_inst(addis0s01);
+        lbb0_15.push_inst(addia3a34);
+        lbb0_15.push_inst(bnea2s0lbb0_14);
+
+        let mut bb16 = Block::new("bb16".into());
+        let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into()));
+        let jlbb0_2 = Inst::Jmp(JmpInst::new("LBB0_2".into()));
+        bb16.push_inst(mvs0a2);
+        bb16.push_inst(jlbb0_2);
+
+        let lbb0_17 = Block::new("LBB0_17".into());
+        // let lia00 = Inst::Li(LiInst::new(REG_A0.into(), (0).into()));
+    }
+}
diff --git a/src/ch2/sizeof.rs b/src/ch2/sizeof.rs
deleted file mode 100644
index a15c5ed..0000000
--- a/src/ch2/sizeof.rs
+++ /dev/null
@@ -1,24 +0,0 @@
-#[cfg(test)]
-pub mod tests {
-    use compiler::backend::*;
-
-    #[test]
-    pub fn quicksort() {
-        let mut bb0 = Block::new("bb0".into());
-        let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
-        let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
-        let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
-        let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
-        let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
-        let bgea1a2lbb0_17 = Inst::Branch(
-            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
-        );
-        bb0.push_inst(addispsp_32);
-        bb0.push_inst(sdra24sp);
-        bb0.push_inst(sds016sp);
-        bb0.push_inst(sds18sp);
-        bb0.push_inst(sds20sp);
-        bb0.push_inst(bgea1a2lbb0_17);
-        println!("{:?}", bb0.gen_asm());
-    }
-}
diff --git a/src/main.rs b/src/main.rs
index f327c37..7bc91a4 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -4,24 +4,4 @@ use std::{ fs::File, io::Write };
 
 use compiler::backend::*;
 
-fn main() {
-    let mut bb0 = Block::new("bb0".into());
-    let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
-    let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
-    let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
-    let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
-    let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
-    let bgea1a2lbb0_17 = Inst::Branch(
-        BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
-    );
-    bb0.push_inst(addispsp_32);
-    bb0.push_inst(sdra24sp);
-    bb0.push_inst(sds016sp);
-    bb0.push_inst(sds18sp);
-    bb0.push_inst(sds20sp);
-    bb0.push_inst(bgea1a2lbb0_17);
-    let asm = bb0.gen_asm();
-
-    let mut file = File::create("output.s").expect("Unable to create file");
-    let _ = file.write(asm.as_bytes()).expect("Unable to write data");
-}
+fn main() {}