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backend_module
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modified: src/ch2/mod.rs 

deleted:    src/ch2/size.rs
	new file:   src/ch2/sizeof.rs
	modified:   src/main.rs
This commit is contained in:
wangfiox 2024-06-10 14:37:19 +08:00
parent 606ee0a1a0
commit 7caa6a5f08
5 changed files with 56 additions and 27 deletions
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7
output.s Normal file
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@ -0,0 +1,7 @@
bb0:
add sp,sp,-32
sd ra,24(sp)
sd s0,16(sp)
sd s1,8(sp)
sd s2,0(sp)
bge a1,a2,LBB0_17

4
src/ch2/mod.rs
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@ -1,3 +1,3 @@
mod size; mod sizeof;
pub use size::*; pub use sizeof::*;

24
src/ch2/size.rs
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@ -1,24 +0,0 @@
#[cfg(test)]
pub mod tests {
use compiler::backend::*;
#[test]
pub fn sizeof() {
let addispsp_32 = AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into());
let sdra24sp = SdInst::new(REG_RA.into(), (24).into(), REG_SP.into());
let sds016sp = SdInst::new(REG_S0.into(), (16).into(), REG_SP.into());
let addis0sp32 = AddInst::new(REG_S0.into(), REG_SP.into(), (32).into());
let lia55 = AddInst::new(REG_A5.into(), REG_ZERO.into(), (55).into());
let swa5_20s0 = SdInst::new(REG_A5.into(), (-20).into(), REG_S0.into());
let lia54 = AddInst::new(REG_A5.into(), REG_ZERO.into(), (4).into());
let swa5_24s0 = SdInst::new(REG_A5.into(), (-24).into(), REG_S0.into());
let lia50 = AddInst::new(REG_A5.into(), REG_ZERO.into(), (0).into());
let mva0a5 = MvInst::new(REG_A0.into(), REG_A5.into());
let ldra24sp = LdInst::new(REG_RA.into(), (24).into(), REG_SP.into());
let addispsp32 = AddInst::new(REG_SP.into(), REG_SP.into(), (32).into());
let addispsp32 = AddInst::new(REG_SP.into(), REG_SP.into(), (32).into());
let jrra = JmpInst::new(REG_RA.into());
}
}

24
src/ch2/sizeof.rs Normal file
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@ -0,0 +1,24 @@
#[cfg(test)]
pub mod tests {
use compiler::backend::*;
#[test]
pub fn quicksort() {
let mut bb0 = Block::new("bb0".into());
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
let bgea1a2lbb0_17 = Inst::Branch(
BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
);
bb0.push_inst(addispsp_32);
bb0.push_inst(sdra24sp);
bb0.push_inst(sds016sp);
bb0.push_inst(sds18sp);
bb0.push_inst(sds20sp);
bb0.push_inst(bgea1a2lbb0_17);
println!("{:?}", bb0.gen_asm());
}
}

24
src/main.rs
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@ -1,5 +1,27 @@
mod ch2; mod ch2;
use std::{ fs::File, io::Write };
use compiler::backend::*;
fn main() { fn main() {
println!("Hello, world!"); let mut bb0 = Block::new("bb0".into());
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
let bgea1a2lbb0_17 = Inst::Branch(
BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
);
bb0.push_inst(addispsp_32);
bb0.push_inst(sdra24sp);
bb0.push_inst(sds016sp);
bb0.push_inst(sds18sp);
bb0.push_inst(sds20sp);
bb0.push_inst(bgea1a2lbb0_17);
let asm = bb0.gen_asm();
let mut file = File::create("output.s").expect("Unable to create file");
let _ = file.write(asm.as_bytes()).expect("Unable to write data");
} }