modified: Cargo.lock
modified: hitc modified: src/ch2/quicksort.rs
This commit is contained in:
wangfiox
parent
8f796fc50d
commit
96509a0252
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@ -2,6 +2,15 @@
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# It is not intended for manual editing.
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version = 3
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[[package]]
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name = "aho-corasick"
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version = "1.1.3"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "8e60d3430d3a69478ad0993f19238d2df97c507009a52b3c10addcd7f6bcb916"
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dependencies = [
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"memchr",
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]
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[[package]]
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name = "atty"
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version = "0.2.14"
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@ -38,6 +47,12 @@ version = "2.5.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "cf4b9d6a944f767f8e5e0db018570623c85f3d925ac718db4e06d0187adb21c1"
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[[package]]
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name = "cc"
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version = "1.0.99"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "96c51067fd44124faa7f870b4b1c969379ad32b2ba805aa959430ceaa384f695"
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[[package]]
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name = "cfg-if"
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version = "1.0.0"
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@ -159,6 +174,7 @@ version = "0.1.0"
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dependencies = [
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"clap",
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"lazy_static",
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"llvm-ir",
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"once_cell",
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"rand",
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"rayon",
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@ -214,6 +230,36 @@ version = "0.4.14"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89"
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[[package]]
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name = "llvm-ir"
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version = "0.10.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "434db35c1dc3bce4d16bb60c4f6a57587dfa8224ba92fc080fde38782c35fc90"
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dependencies = [
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"either",
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"llvm-sys",
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"log",
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]
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[[package]]
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name = "llvm-sys"
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version = "160.1.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "49f9888529887dfda6c59e20f0e0727b17e826cd54ae1ddf0d4c83850fa23b69"
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dependencies = [
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"cc",
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"lazy_static",
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"libc",
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"regex",
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"semver",
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]
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[[package]]
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name = "log"
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version = "0.4.21"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "90ed8c1e510134f979dbc4f070f87d4313098b704861a105fe34231c70a3901c"
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[[package]]
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name = "memchr"
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version = "2.7.2"
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@ -306,6 +352,35 @@ dependencies = [
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"crossbeam-utils",
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]
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[[package]]
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name = "regex"
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version = "1.10.5"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b91213439dad192326a0d7c6ee3955910425f441d7038e0d6933b0aec5c4517f"
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dependencies = [
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"aho-corasick",
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"memchr",
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"regex-automata",
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"regex-syntax",
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]
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[[package]]
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name = "regex-automata"
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version = "0.4.7"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "38caf58cc5ef2fed281f89292ef23f6365465ed9a41b7a7754eb4e26496c92df"
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dependencies = [
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"aho-corasick",
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"memchr",
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"regex-syntax",
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]
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[[package]]
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name = "regex-syntax"
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version = "0.8.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b"
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[[package]]
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name = "rustix"
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version = "0.38.34"
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@ -325,6 +400,12 @@ version = "1.0.18"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "f3cb5ba0dc43242ce17de99c180e96db90b235b8a9fdc9543c96d2209116bd9f"
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[[package]]
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name = "semver"
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version = "1.0.23"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b"
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[[package]]
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name = "serde"
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version = "1.0.203"
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2
hitc
2
hitc
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@ -1 +1 @@
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Subproject commit 4c0a5494241520872bbbb73b13c9c6be622bac7b
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Subproject commit c8aece5ed50bd5e19492f51003a25f423a3ca7bd
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@ -1,11 +1,9 @@
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#[cfg(test)]
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pub mod tests {
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use compiler::backend::*;
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use compiler::{ backend::*, middle::ir::instruction::binary_inst::Add };
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#[test]
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pub fn quicksort_example() {
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let mut quickSort = Func::new("QuickSort".into(), Vec::new());
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let mut entry = Block::new("entry".into());
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let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
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let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
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@ -15,18 +13,11 @@ pub mod tests {
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let bgea1a2lbb0_17 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
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);
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entry.push_inst(addispsp_32);
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entry.push_inst(sdra24sp);
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entry.push_inst(sds016sp);
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entry.push_inst(sds18sp);
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entry.push_inst(sds20sp);
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entry.push_inst(bgea1a2lbb0_17);
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entry.extend_insts(vec![addispsp_32, sdra24sp, sds016sp, sds18sp, sds20sp, bgea1a2lbb0_17]);
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let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
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let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
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let jlbb0_3 = Inst::Jmp(JmpInst::new("LBB0_3".into()));
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entry.push_inst(mvs2a2);
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entry.push_inst(mvs1a0);
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entry.push_inst(jlbb0_3);
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entry.extend_insts(vec![mvs2a2, mvs1a0, jlbb0_3]);
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let mut lbb0_2 = Block::new("lbb0_2".into());
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let sllia2s02 = Inst::SLL(SllInst::new(REG_A2.into(), REG_S0.into(), (2).into()));
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@ -39,146 +30,121 @@ pub mod tests {
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let bgea1s2lbb0_17 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into())
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);
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lbb0_2.push_inst(sllia2s02);
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lbb0_2.push_inst(adda2a2s1);
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lbb0_2.push_inst(swa00a2);
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lbb0_2.push_inst(addia2s0_1);
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lbb0_2.push_inst(mva0s1);
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lbb0_2.push_inst(callquicksort);
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lbb0_2.push_inst(addia1s01);
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lbb0_2.push_inst(bgea1s2lbb0_17);
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lbb0_2.extend_insts(
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vec![
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sllia2s02,
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adda2a2s1,
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swa00a2,
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addia2s0_1,
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mva0s1,
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callquicksort,
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addia1s01,
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bgea1s2lbb0_17
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]
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);
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let mut lbb0_3 = Block::new("LBB0_3".into());
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let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
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let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into()));
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// let lwa00a0 = Inst::
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let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
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let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
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let bgea1s2lbb0_2 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into())
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);
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lbb0_3.push_inst(sllia0a12);
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lbb0_3.push_inst(adda0a0s1);
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// lbb0_3.push_inst(lwa00a0)
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lbb0_3.push_inst(mvs0a1);
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lbb0_3.push_inst(bgea1s2lbb0_2);
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lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, lwa00a0, mvs0a1, bgea1s2lbb0_2]);
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let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
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let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into()));
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let jlbb0_7 = Inst::Jmp(JmpInst::new("LBB0_7".into()));
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lbb0_3.push_inst(mvs0a1);
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lbb0_3.push_inst(mva2s2);
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lbb0_3.push_inst(jlbb0_7);
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lbb0_3.extend_insts(vec![mvs0a1, mva2s2, jlbb0_7]);
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let mut lbb0_5 = Block::new("LBB0_5".into());
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let sllis3s22 = Inst::SLL(SllInst::new(REG_S3.into(), REG_S2.into(), (2).into()));
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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let swa40a3 = Inst::Sd(SdInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
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let swa40a3 = Inst::Sw(SwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
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let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
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lbb0_5.push_inst(sllis3s22);
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lbb0_5.push_inst(adda3a3s1);
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lbb0_5.push_inst(swa40a3);
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lbb0_5.push_inst(addia2a2_1);
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lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, swa40a3, addia2a2_1]);
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let mut llb0_6 = Block::new("LBB0_6".into());
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let bges0a2lbb0_2 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into())
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);
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llb0_6.push_inst(bges0a2lbb0_2);
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llb0_6.extend_insts(vec![bges0a2lbb0_2]);
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let mut lbb0_7 = Block::new("LBB0_7".into());
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let bges0a2lbb0_11 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into())
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);
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lbb0_7.push_inst(bges0a2lbb0_11);
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lbb0_7.extend_insts(vec![bges0a2lbb0_11]);
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let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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let mva4a2 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A2.into()));
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lbb0_7.push_inst(sllia3a22);
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lbb0_7.push_inst(adda3a3s1);
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lbb0_7.push_inst(mva4a2);
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lbb0_7.extend_insts(vec![sllia3a22, adda3a3s1, mva4a2]);
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let mut lbb0_9 = Block::new("LBB0_9".into());
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let lwa50a3 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let blta5a0lbb0_12 = Inst::Branch(
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BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into())
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);
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lbb0_9.push_inst(lwa50a3);
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lbb0_9.push_inst(blta5a0lbb0_12);
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lbb0_9.extend_insts(vec![lwa50a3, blta5a0lbb0_12]);
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let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into()));
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let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
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let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into()));
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let blts0a4lbb0_9 = Inst::Branch(
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BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into())
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);
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lbb0_9.push_inst(addia4a4_1);
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lbb0_9.push_inst(addia2a2_1);
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lbb0_9.push_inst(addia3a3_4);
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lbb0_9.push_inst(blts0a4lbb0_9);
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lbb0_9.extend_insts(vec![addia4a4_1, addia2a2_1, addia3a3_4, blts0a4lbb0_9]);
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let mut lbb0_11 = Block::new("LBB0_11".into());
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let bges0a2lbb0_6 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
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);
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let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into()));
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lbb0_11.push_inst(bges0a2lbb0_6);
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lbb0_11.push_inst(jlbb0_13);
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lbb0_11.extend_insts(vec![bges0a2lbb0_6, jlbb0_13]);
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let mut lbb0_12 = Block::new("LBB0_12".into());
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let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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let swa50a3 = Inst::Sd(SdInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
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let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
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let bges0a2lbb0_6 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
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);
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lbb0_12.push_inst(sllia3s02);
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lbb0_12.push_inst(adda3a3s1);
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lbb0_12.push_inst(swa50a3);
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lbb0_12.push_inst(addis0s01);
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lbb0_12.push_inst(bges0a2lbb0_6);
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lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, swa50a3, addis0s01, bges0a2lbb0_6]);
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|
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let mut lbb0_13 = Block::new("LBB0_13".into());
|
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let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
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let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
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lbb0_13.push_inst(sllia3s02);
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lbb0_13.push_inst(adda3a3s1);
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lbb0_13.extend_insts(vec![sllia3s02, adda3a3s1]);
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let mut lbb0_14 = Block::new("LBB0_14".into());
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// lw a4, 0(a3)
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let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
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let bgea4a0lbb0_5 = Inst::Branch(
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BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into())
|
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);
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lbb0_14.push_inst(bgea4a0lbb0_5);
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lbb0_14.extend_insts(vec![lwa40a3, bgea4a0lbb0_5]);
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// push_inst lw
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let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
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let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into()));
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let bnea2s0lbb0_14 = Inst::Branch(
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BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into())
|
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);
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lbb0_14.push_inst(addis0s01);
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lbb0_14.push_inst(addia3a34);
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lbb0_14.push_inst(bnea2s0lbb0_14);
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lbb0_14.extend_insts(vec![addis0s01, addia3a34, bnea2s0lbb0_14]);
|
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let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into()));
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let jlbb0_2 = Inst::Jmp(JmpInst::new("LBB0_2".into()));
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lbb0_14.push_inst(mvs0a2);
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lbb0_14.push_inst(jlbb0_2);
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lbb0_14.extend_insts(vec![mvs0a2, jlbb0_2]);
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|
||||
let mut lbb0_17 = Block::new("LBB0_17".into());
|
||||
// let lia00 = Inst::Li(LiInst::new(REG_A0.into(), (0).into()));
|
||||
let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
// li
|
||||
lbb0_17.push_inst(ldra24sp);
|
||||
lbb0_17.push_inst(lds016sp);
|
||||
lbb0_17.push_inst(lds18sp);
|
||||
lbb0_17.push_inst(lds20sp);
|
||||
lbb0_17.push_inst(addispsp32);
|
||||
lbb0_17.push_inst(ret);
|
||||
lbb0_17.extend_insts(vec![lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret]);
|
||||
|
||||
quickSort.push_bb(entry);
|
||||
let mut quickSort = Func::new("QuickSort".into(), Vec::new(), entry);
|
||||
quickSort.push_bb(lbb0_2);
|
||||
quickSort.push_bb(lbb0_3);
|
||||
quickSort.push_bb(lbb0_5);
|
||||
|
|
@ -191,8 +157,68 @@ pub mod tests {
|
|||
quickSort.push_bb(lbb0_14);
|
||||
quickSort.push_bb(lbb0_17);
|
||||
|
||||
quickSort.set_entry("entry".into());
|
||||
let asm = quickSort.gen_asm();
|
||||
print!("{}", asm);
|
||||
// main: # @main
|
||||
// addi sp, sp, -80
|
||||
// sd ra, 72(sp) # 8-byte Folded Spill
|
||||
// sd s0, 64(sp) # 8-byte Folded Spill
|
||||
// sd s1, 56(sp) # 8-byte Folded Spill
|
||||
// sd s2, 48(sp) # 8-byte Folded Spill
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let lia29 = Inst::Add(AddInst::new(REG_A2.into(), REG_ZERO.into(), (9).into()));
|
||||
let lia10 = Inst::Add(AddInst::new(REG_A1.into(), REG_ZERO.into(), (0).into()));
|
||||
let sdra16sp = Inst::Sd(SdInst::new(REG_RA.into(), (72).into(), REG_SP.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S0.into(), (64).into(), REG_SP.into()));
|
||||
let sds10sp = Inst::Sd(SdInst::new(REG_S1.into(), (56).into(), REG_SP.into()));
|
||||
let sds124sp = Inst::Sd(SdInst::new(REG_S2.into(), (48).into(), REG_SP.into()));
|
||||
// # %bb.0:
|
||||
// .Lpcrel_hi0:
|
||||
// auipc s2, %pcrel_hi(n)
|
||||
// li a0, 10
|
||||
// sw a0, %pcrel_lo(.Lpcrel_hi0)(s2)
|
||||
// li a0, 4
|
||||
// sw a0, 8(sp)
|
||||
// li a0, 3
|
||||
// sw a0, 12(sp)
|
||||
// li a0, 9
|
||||
// sw a0, 16(sp)
|
||||
// li a0, 2
|
||||
// sw a0, 20(sp)
|
||||
// sw zero, 24(sp)
|
||||
// li a0, 1
|
||||
// sw a0, 28(sp)
|
||||
// li a0, 6
|
||||
// sw a0, 32(sp)
|
||||
// li a0, 5
|
||||
// sw a0, 36(sp)
|
||||
// li a0, 7
|
||||
// sw a0, 40(sp)
|
||||
// li a0, 8
|
||||
// sw a0, 44(sp)
|
||||
// addi a0, sp, 8
|
||||
// li a2, 9
|
||||
// addi s1, sp, 8
|
||||
// li a1, 0
|
||||
// call QuickSort
|
||||
// li s0, 0
|
||||
// .LBB1_1: # =>This Inner Loop Header: Depth=1
|
||||
// lw a0, 0(s1)
|
||||
// call putint@plt
|
||||
// li a0, 10
|
||||
// call putch@plt
|
||||
// li a0, 10
|
||||
// call putch@plt
|
||||
// lw a0, %pcrel_lo(.Lpcrel_hi0)(s2)
|
||||
// addi s0, s0, 1
|
||||
// addi s1, s1, 4
|
||||
// blt s0, a0, .LBB1_1
|
||||
// # %bb.2:
|
||||
// li a0, 0
|
||||
// ld ra, 72(sp) # 8-byte Folded Reload
|
||||
// ld s0, 64(sp) # 8-byte Folded Reload
|
||||
// ld s1, 56(sp) # 8-byte Folded Reload
|
||||
// ld s2, 48(sp) # 8-byte Folded Reload
|
||||
// addi sp, sp, 80
|
||||
// ret
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue