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wangfiox
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checksum = "7253ab4de971e72fb7be983802300c30b5a7f0c2e56fab8abfc6a214307c0094"
|
||||
dependencies = [
|
||||
"serde_derive",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "serde_derive"
|
||||
version = "1.0.203"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "500cbc0ebeb6f46627f50f3f5811ccf6bf00643be300b4c3eabc0ef55dc5b5ba"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
"syn",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "serde_yaml"
|
||||
version = "0.9.34+deprecated"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "6a8b1a1a2ebf674015cc02edccce75287f1a0130d394307b36743c2f5d504b47"
|
||||
dependencies = [
|
||||
"indexmap 2.2.6",
|
||||
"itoa",
|
||||
"ryu",
|
||||
"serde",
|
||||
"unsafe-libyaml",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "strsim"
|
||||
version = "0.10.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "73473c0e59e6d5812c5dfe2a064a6444949f089e20eec9a2e5506596494e4623"
|
||||
|
||||
[[package]]
|
||||
name = "syn"
|
||||
version = "2.0.66"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
"unicode-ident",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "tempfile"
|
||||
version = "3.10.1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "85b77fafb263dd9d05cbeac119526425676db3784113aa9295c88498cbf8bff1"
|
||||
dependencies = [
|
||||
"cfg-if",
|
||||
"fastrand",
|
||||
"rustix",
|
||||
"windows-sys",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "termcolor"
|
||||
version = "1.4.1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "06794f8f6c5c898b3275aebefa6b8a1cb24cd2c6c79397ab15774837a0bc5755"
|
||||
dependencies = [
|
||||
"winapi-util",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "textwrap"
|
||||
version = "0.16.1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "23d434d3f8967a09480fb04132ebe0a3e088c173e6d0ee7897abbdf4eab0f8b9"
|
||||
|
||||
[[package]]
|
||||
name = "thiserror"
|
||||
version = "1.0.61"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "c546c80d6be4bc6a00c0f01730c08df82eaa7a7a61f11d656526506112cc1709"
|
||||
dependencies = [
|
||||
"thiserror-impl",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "thiserror-impl"
|
||||
version = "1.0.61"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "46c3384250002a6d5af4d114f2845d37b57521033f30d5c3f46c4d70e1197533"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
"syn",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "typed-arena"
|
||||
version = "2.0.2"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "6af6ae20167a9ece4bcb41af5b80f8a1f1df981f6391189ce00fd257af04126a"
|
||||
|
||||
[[package]]
|
||||
name = "unicode-ident"
|
||||
version = "1.0.12"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
|
||||
|
||||
[[package]]
|
||||
name = "unsafe-libyaml"
|
||||
version = "0.2.11"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "673aac59facbab8a9007c7f6108d11f63b603f7cabff99fabf650fea5c32b861"
|
||||
|
||||
[[package]]
|
||||
name = "wasi"
|
||||
version = "0.11.0+wasi-snapshot-preview1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423"
|
||||
|
||||
[[package]]
|
||||
name = "winapi"
|
||||
version = "0.3.9"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419"
|
||||
dependencies = [
|
||||
"winapi-i686-pc-windows-gnu",
|
||||
"winapi-x86_64-pc-windows-gnu",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "winapi-i686-pc-windows-gnu"
|
||||
version = "0.4.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
|
||||
|
||||
[[package]]
|
||||
name = "winapi-util"
|
||||
version = "0.1.8"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "4d4cc384e1e73b93bafa6fb4f1df8c41695c8a91cf9c4c64358067d15a7b6c6b"
|
||||
dependencies = [
|
||||
"windows-sys",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "winapi-x86_64-pc-windows-gnu"
|
||||
version = "0.4.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
|
||||
|
||||
[[package]]
|
||||
name = "windows-sys"
|
||||
version = "0.52.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d"
|
||||
dependencies = [
|
||||
"windows-targets",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "windows-targets"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "6f0713a46559409d202e70e28227288446bf7841d3211583a4b53e3f6d96e7eb"
|
||||
dependencies = [
|
||||
"windows_aarch64_gnullvm",
|
||||
"windows_aarch64_msvc",
|
||||
"windows_i686_gnu",
|
||||
"windows_i686_gnullvm",
|
||||
"windows_i686_msvc",
|
||||
"windows_x86_64_gnu",
|
||||
"windows_x86_64_gnullvm",
|
||||
"windows_x86_64_msvc",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_gnullvm"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "7088eed71e8b8dda258ecc8bac5fb1153c5cffaf2578fc8ff5d61e23578d3263"
|
||||
|
||||
[[package]]
|
||||
name = "windows_aarch64_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "9985fd1504e250c615ca5f281c3f7a6da76213ebd5ccc9561496568a2752afb6"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnu"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "88ba073cf16d5372720ec942a8ccbf61626074c6d4dd2e745299726ce8b89670"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_gnullvm"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "87f4261229030a858f36b459e748ae97545d6f1ec60e5e0d6a3d32e0dc232ee9"
|
||||
|
||||
[[package]]
|
||||
name = "windows_i686_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "db3c2bf3d13d5b658be73463284eaf12830ac9a26a90c717b7f771dfe97487bf"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnu"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "4e4246f76bdeff09eb48875a0fd3e2af6aada79d409d33011886d3e1581517d9"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_gnullvm"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "852298e482cd67c356ddd9570386e2862b5673c85bd5f88df9ab6802b334c596"
|
||||
|
||||
[[package]]
|
||||
name = "windows_x86_64_msvc"
|
||||
version = "0.52.5"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "bec47e5bfd1bff0eeaf6d8b485cc1074891a197ab4225d504cb7a1ab88b02bf0"
|
||||
|
||||
[[package]]
|
||||
name = "winnow"
|
||||
version = "0.6.13"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "59b5e5f6c299a3c7890b876a2a587f3115162487e704907d9b6cd29473052ba1"
|
||||
dependencies = [
|
||||
"memchr",
|
||||
]
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
[package]
|
||||
name = "backend_module"
|
||||
version = "0.1.0"
|
||||
edition = "2021"
|
||||
|
||||
[dependencies]
|
||||
hitc = { path = "./hitc" }
|
||||
|
|
@ -0,0 +1 @@
|
|||
Subproject commit f3b9eefa3cb53f181d09328a66efeb3343ea7d3f
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
bb0:
|
||||
add sp,sp,-32
|
||||
sd ra,24(sp)
|
||||
sd s0,16(sp)
|
||||
sd s1,8(sp)
|
||||
sd s2,0(sp)
|
||||
bge a1,a2,LBB0_17
|
||||
|
|
@ -0,0 +1,276 @@
|
|||
pub mod tests {
|
||||
use compiler::backend::Inst::{ Call, Jmp };
|
||||
use compiler::backend::{
|
||||
AddInst,
|
||||
Block,
|
||||
BranchInst,
|
||||
BranchOp,
|
||||
CallInst,
|
||||
Func,
|
||||
Inst,
|
||||
JmpInst,
|
||||
LdInst,
|
||||
LwInst,
|
||||
Module,
|
||||
MvInst,
|
||||
SdInst,
|
||||
SwInst,
|
||||
REG_A0,
|
||||
REG_A1,
|
||||
REG_A2,
|
||||
REG_A3,
|
||||
REG_A4,
|
||||
REG_A5,
|
||||
REG_RA,
|
||||
REG_S0,
|
||||
REG_S1,
|
||||
REG_S2,
|
||||
REG_SP,
|
||||
REG_ZERO,
|
||||
};
|
||||
use compiler::middle::ir::InstPtr;
|
||||
|
||||
#[test]
|
||||
pub fn linked() {
|
||||
/* ---------- ---------- createLinkedList ---------- ---------- */
|
||||
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_16 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-16).into()));
|
||||
let lia08 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (-16).into()));
|
||||
let sdra8sp = Inst::Sd(SdInst::new(REG_RA.into(), (8).into(), REG_SP.into()));
|
||||
let sds00sp = Inst::Sd(SdInst::new(REG_S0.into(), (0).into(), REG_SP.into()));
|
||||
let callmalloc1 = Inst::Call(CallInst::new("malloc@plt".into()));
|
||||
let beqa0zerol2 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L2".into())
|
||||
);
|
||||
let mvs0a0 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A0.into()));
|
||||
let lia016 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (16).into()));
|
||||
let callmalloc2 = Inst::Call(CallInst::new("malloc@plt".into()));
|
||||
let sda00s0 = Inst::Sd(SdInst::new(REG_A0.into(), (0).into(), REG_S0.into()));
|
||||
let beqa0zerol3 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L3".into())
|
||||
);
|
||||
let sdzero8a0 = Inst::Sd(SdInst::new(REG_ZERO.into(), (8).into(), REG_A0.into()));
|
||||
entry.extend_insts(
|
||||
vec![
|
||||
addispsp_16,
|
||||
lia08,
|
||||
sdra8sp,
|
||||
sds00sp,
|
||||
callmalloc1,
|
||||
beqa0zerol2,
|
||||
mvs0a0,
|
||||
lia016,
|
||||
callmalloc2,
|
||||
sda00s0,
|
||||
beqa0zerol3,
|
||||
sdzero8a0
|
||||
]
|
||||
);
|
||||
// L1
|
||||
let mut l1 = Block::new("L1".into());
|
||||
let ldra8sp = Inst::Ld(LdInst::new(REG_RA.into(), (8).into(), REG_SP.into()));
|
||||
let mva0s0 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S0.into()));
|
||||
let lds00sp = Inst::Ld(LdInst::new(REG_S0.into(), (0).into(), REG_SP.into()));
|
||||
let addispsp16 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (8).into()));
|
||||
let ret = Inst::Ret;
|
||||
l1.extend_insts(vec![ldra8sp, mva0s0, lds00sp, addispsp16, ret]);
|
||||
let mut l3 = Block::new("L3".into());
|
||||
let mva0s0 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S0.into()));
|
||||
let callfree = Inst::Call(CallInst::new("free@plt".into()));
|
||||
l3.extend_insts(vec![mva0s0, callfree]);
|
||||
let mut l2 = Block::new("l2".into());
|
||||
let lis00 = Inst::Add(AddInst::new(REG_S0.into(), REG_ZERO.into(), (0).into()));
|
||||
let jl1 = Inst::Jmp(JmpInst::new("L1".into()));
|
||||
l2.extend_insts(vec![lis00, jl1]);
|
||||
|
||||
let mut createLinkedList = Func::new("createLinkedList".into(), Vec::new(), entry);
|
||||
createLinkedList.push_bb(l1);
|
||||
createLinkedList.push_bb(l2);
|
||||
createLinkedList.push_bb(l3);
|
||||
|
||||
/* ---------- ---------- destroyLinkedList ---------- ---------- */
|
||||
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds00a0 = Inst::Ld(LdInst::new(REG_SP.into(), (0).into(), REG_A0.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
|
||||
let beqs0zerol31 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Beq, REG_S0.into(), REG_ZERO.into(), "L31".into())
|
||||
);
|
||||
entry.extend_insts(
|
||||
vec![addispsp_32, sds016sp, lds00a0, sds18sp, sdra24sp, mvs1a0, beqs0zerol31]
|
||||
);
|
||||
|
||||
let mut l32 = Block::new("L32".into());
|
||||
let mva0s0 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S0.into()));
|
||||
let lds08s0 = Inst::Ld(LdInst::new(REG_S0.into(), (8).into(), REG_S0.into()));
|
||||
let callfree = Inst::Call(CallInst::new("free@plt".into()));
|
||||
let bnes0zerol32 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_ZERO.into(), "L32".into())
|
||||
);
|
||||
l32.extend_insts(vec![mva0s0, lds08s0, callfree, bnes0zerol32]);
|
||||
|
||||
let mut l31 = Block::new("L32".into());
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
//let tailfree = Inst::
|
||||
l31.extend_insts(vec![lds016sp, ldra24sp, mva0s1, lds18sp, addispsp32]);
|
||||
|
||||
let mut destroyLinkedList = Func::new("destroyLinkedList".into(), Vec::new(), entry);
|
||||
destroyLinkedList.push_bb(l32);
|
||||
destroyLinkedList.push_bb(l31);
|
||||
|
||||
/* ---------- ---------- findNode ---------- ---------- */
|
||||
let mut entry = Block::new("findNode".into());
|
||||
let lda50a0 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
|
||||
let lda08a5 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A5.into()));
|
||||
// bne a0,zero,.L22
|
||||
let bnea0zerol22 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A0.into(), REG_ZERO.into(), "L22".into())
|
||||
);
|
||||
let jl29 = Inst::Jmp(JmpInst::new("L29".into()));
|
||||
entry.extend_insts(vec![lda50a0, lda08a5, bnea0zerol22, jl29]);
|
||||
|
||||
//
|
||||
//.L24:
|
||||
let mut l24 = Block::new("L24".into());
|
||||
let lda08a0 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A0.into()));
|
||||
let beqa0zerol21 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L21".into())
|
||||
);
|
||||
l24.extend_insts(vec![lda08a0, beqa0zerol21]);
|
||||
|
||||
let mut l22 = Block::new("L22".into());
|
||||
let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
|
||||
let bnea5a1l24 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A5.into(), REG_A1.into(), "L24".into())
|
||||
);
|
||||
l22.extend_insts(vec![lwa50a0, bnea5a1l24]);
|
||||
|
||||
let mut l21 = Block::new("L21".into());
|
||||
let ret = Inst::Ret;
|
||||
l21.extend_insts(vec![ret]);
|
||||
|
||||
let mut l29 = Block::new("L21".into());
|
||||
let ret = Inst::Ret;
|
||||
l29.extend_insts(vec![ret]);
|
||||
|
||||
let mut findNode = Func::new("findNode".into(), Vec::new(), entry);
|
||||
findNode.push_bb(l24);
|
||||
findNode.push_bb(l22);
|
||||
findNode.push_bb(l21);
|
||||
findNode.push_bb(l29);
|
||||
|
||||
/* ---------- ---------- deleteNode ---------- ---------- */
|
||||
|
||||
//deleteNode:
|
||||
let mut entry = Block::new("entry".into());
|
||||
let lda00a0 = Inst::Ld(LdInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
|
||||
let jl16 = Inst::Jmp(JmpInst::new("L16".into()));
|
||||
entry.extend_insts(vec![lda00a0, jl16]);
|
||||
|
||||
//.L20:
|
||||
let mut l20 = Block::new("L20".into());
|
||||
let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
|
||||
let beqa5a1L19 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Beq, REG_A5.into(), REG_A1.into(), "L19".into())
|
||||
);
|
||||
l20.extend_insts(vec![lwa50a0, beqa5a1L19]);
|
||||
|
||||
//.L16:
|
||||
let mut l16 = Block::new("L16".into());
|
||||
let mva4a0 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A0.into()));
|
||||
let lda08a0 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A0.into()));
|
||||
let bnea0zeroL20 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A0.into(), REG_ZERO.into(), "L20".into())
|
||||
);
|
||||
let ret = Inst::Ret;
|
||||
l16.extend_insts(vec![mva4a0, lda08a0, bnea0zeroL20, ret]);
|
||||
|
||||
let mut l19 = Block::new("L19".into());
|
||||
let lda58a0 = Inst::Ld(LdInst::new(REG_A5.into(), (8).into(), REG_A0.into()));
|
||||
let sda58a4 = Inst::Sd(SdInst::new(REG_A5.into(), (8).into(), REG_A4.into()));
|
||||
// tail free@plt
|
||||
l19.extend_insts(vec![lda58a0, sda58a4]);
|
||||
|
||||
let mut deleteNode = Func::new("deleteNode".into(), Vec::new(), entry);
|
||||
deleteNode.push_bb(l20);
|
||||
deleteNode.push_bb(l16);
|
||||
deleteNode.push_bb(l19);
|
||||
|
||||
/* ---------- ---------- insertNode ---------- ---------- */
|
||||
//insertNode:
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
|
||||
let lia016 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (16).into()));
|
||||
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
|
||||
let callmalloc = Inst::Call(CallInst::new("malloc@plt".into()));
|
||||
let lda50s1 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_S1.into()));
|
||||
let sws00a0 = Inst::Sw(SwInst::new(REG_S0.into(), (0).into(), REG_A0.into()));
|
||||
let sdzero8a0 = Inst::Sd(SdInst::new(REG_ZERO.into(), (8).into(), REG_A0.into()));
|
||||
entry.extend_insts(
|
||||
vec![
|
||||
addispsp_32,
|
||||
sds18sp,
|
||||
mvs1a0,
|
||||
lia016,
|
||||
sds016sp,
|
||||
sdra24sp,
|
||||
mvs0a1,
|
||||
callmalloc,
|
||||
lda50s1,
|
||||
sws00a0,
|
||||
sdzero8a0
|
||||
]
|
||||
);
|
||||
|
||||
let mut l11 = Block::new("L11".into());
|
||||
let mva4a5 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A5.into()));
|
||||
let lda58a5 = Inst::Ld(LdInst::new(REG_A5.into(), (8).into(), REG_A5.into()));
|
||||
let bnea5zeroL11 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A5.into(), REG_ZERO.into(), "L11".into())
|
||||
);
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let sds08sp = Inst::Sd(SdInst::new(REG_S0.into(), (8).into(), REG_A4.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
l11.extend_insts(
|
||||
vec![
|
||||
mva4a5,
|
||||
lda58a5,
|
||||
bnea5zeroL11,
|
||||
ldra24sp,
|
||||
lds016sp,
|
||||
sds08sp,
|
||||
lds18sp,
|
||||
addispsp32,
|
||||
ret
|
||||
]
|
||||
);
|
||||
|
||||
let mut insertNode = Func::new("insertNode".into(), Vec::new(), entry);
|
||||
insertNode.push_bb(l11);
|
||||
|
||||
//let linkli =
|
||||
let main_module = Module {
|
||||
name: "main".into(),
|
||||
global: Vec::new(),
|
||||
funcs: vec![insertNode, deleteNode, findNode, destroyLinkedList, createLinkedList],
|
||||
entry: None,
|
||||
};
|
||||
print!("{}", main_module.gen_asm());
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
// 定义链表节点结构体
|
||||
typedef struct ListNode {
|
||||
int data; // 数据域
|
||||
struct ListNode *next; // 指向下一个节点的指针
|
||||
} ListNode;
|
||||
|
||||
// 定义链表结构体，这里我们的链表包含一个头结点
|
||||
typedef struct LinkedList {
|
||||
ListNode *head; // 指向头结点的指针
|
||||
} LinkedList;
|
||||
|
||||
// 创建链表，初始化头结点
|
||||
LinkedList *createLinkedList() {
|
||||
LinkedList *list = (LinkedList *)malloc(sizeof(LinkedList));
|
||||
if (list) {
|
||||
list->head = (ListNode *)malloc(sizeof(ListNode)); // 创建头结点
|
||||
if (list->head) {
|
||||
list->head->next = NULL; // 头结点的next指向NULL
|
||||
} else {
|
||||
free(list); // 如果头结点创建失败，释放链表结构体所占内存
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
return list;
|
||||
}
|
||||
|
||||
// 在链表尾部插入节点
|
||||
void insertNode(LinkedList *list, int data) {
|
||||
ListNode *newNode = (ListNode *)malloc(sizeof(ListNode));
|
||||
newNode->data = data;
|
||||
newNode->next = NULL;
|
||||
|
||||
// 找到链表的最后一个节点
|
||||
ListNode *current = list->head;
|
||||
while (current->next != NULL) {
|
||||
current = current->next;
|
||||
}
|
||||
// 将新节点插入到链表尾部
|
||||
current->next = newNode;
|
||||
}
|
||||
|
||||
// 删除链表中的节点
|
||||
void deleteNode(LinkedList *list, int data) {
|
||||
ListNode *current = list->head;
|
||||
ListNode *previous = NULL;
|
||||
while (current->next != NULL && current->next->data != data) {
|
||||
previous = current;
|
||||
current = current->next;
|
||||
}
|
||||
if (current->next != NULL) {
|
||||
ListNode *temp = current->next;
|
||||
current->next = current->next->next;
|
||||
free(temp);
|
||||
}
|
||||
}
|
||||
|
||||
// 查找链表中的节点
|
||||
ListNode *findNode(LinkedList *list, int data) {
|
||||
ListNode *current = list->head->next; // 从第一个实际存储数据的节点开始
|
||||
while (current != NULL && current->data != data) {
|
||||
current = current->next;
|
||||
}
|
||||
return current;
|
||||
}
|
||||
|
||||
// 销毁链表
|
||||
void destroyLinkedList(LinkedList *list) {
|
||||
ListNode *current = list->head;
|
||||
while (current != NULL) {
|
||||
ListNode *temp = current;
|
||||
current = current->next;
|
||||
free(temp);
|
||||
}
|
||||
free(list);
|
||||
}
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
.file "list.c"
|
||||
.option pic
|
||||
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"
|
||||
.attribute unaligned_access, 0
|
||||
.attribute stack_align, 16
|
||||
.text
|
||||
.align 1
|
||||
.globl createLinkedList
|
||||
.type createLinkedList, @function
|
||||
createLinkedList:
|
||||
addi sp,sp,-16
|
||||
li a0,8
|
||||
sd ra,8(sp)
|
||||
sd s0,0(sp)
|
||||
call malloc@plt
|
||||
beq a0,zero,.L2
|
||||
mv s0,a0
|
||||
li a0,16
|
||||
call malloc@plt
|
||||
sd a0,0(s0)
|
||||
beq a0,zero,.L3
|
||||
sd zero,8(a0)
|
||||
.L1:
|
||||
ld ra,8(sp)
|
||||
mv a0,s0
|
||||
ld s0,0(sp)
|
||||
addi sp,sp,16
|
||||
jr ra
|
||||
.L3:
|
||||
mv a0,s0
|
||||
call free@plt
|
||||
.L2:
|
||||
li s0,0
|
||||
j .L1
|
||||
.size createLinkedList, .-createLinkedList
|
||||
.align 1
|
||||
.globl insertNode
|
||||
.type insertNode, @function
|
||||
insertNode:
|
||||
addi sp,sp,-32
|
||||
sd s1,8(sp)
|
||||
mv s1,a0
|
||||
li a0,16
|
||||
sd s0,16(sp)
|
||||
sd ra,24(sp)
|
||||
mv s0,a1
|
||||
call malloc@plt
|
||||
ld a5,0(s1)
|
||||
sw s0,0(a0)
|
||||
sd zero,8(a0)
|
||||
.L11:
|
||||
mv a4,a5
|
||||
ld a5,8(a5)
|
||||
bne a5,zero,.L11
|
||||
ld ra,24(sp)
|
||||
ld s0,16(sp)
|
||||
sd a0,8(a4)
|
||||
ld s1,8(sp)
|
||||
addi sp,sp,32
|
||||
jr ra
|
||||
.size insertNode, .-insertNode
|
||||
.align 1
|
||||
.globl deleteNode
|
||||
.type deleteNode, @function
|
||||
deleteNode:
|
||||
ld a0,0(a0)
|
||||
j .L16
|
||||
.L20:
|
||||
lw a5,0(a0)
|
||||
beq a5,a1,.L19
|
||||
.L16:
|
||||
mv a4,a0
|
||||
ld a0,8(a0)
|
||||
bne a0,zero,.L20
|
||||
ret
|
||||
.L19:
|
||||
ld a5,8(a0)
|
||||
sd a5,8(a4)
|
||||
tail free@plt
|
||||
.size deleteNode, .-deleteNode
|
||||
.align 1
|
||||
.globl findNode
|
||||
.type findNode, @function
|
||||
findNode:
|
||||
ld a5,0(a0)
|
||||
ld a0,8(a5)
|
||||
bne a0,zero,.L22
|
||||
j .L29
|
||||
.L24:
|
||||
ld a0,8(a0)
|
||||
beq a0,zero,.L21
|
||||
.L22:
|
||||
lw a5,0(a0)
|
||||
bne a5,a1,.L24
|
||||
.L21:
|
||||
ret
|
||||
.L29:
|
||||
ret
|
||||
.size findNode, .-findNode
|
||||
.align 1
|
||||
.globl destroyLinkedList
|
||||
.type destroyLinkedList, @function
|
||||
destroyLinkedList:
|
||||
addi sp,sp,-32
|
||||
sd s0,16(sp)
|
||||
ld s0,0(a0)
|
||||
sd s1,8(sp)
|
||||
sd ra,24(sp)
|
||||
mv s1,a0
|
||||
beq s0,zero,.L31
|
||||
.L32:
|
||||
mv a0,s0
|
||||
ld s0,8(s0)
|
||||
call free@plt
|
||||
bne s0,zero,.L32
|
||||
.L31:
|
||||
ld s0,16(sp)
|
||||
ld ra,24(sp)
|
||||
mv a0,s1
|
||||
ld s1,8(sp)
|
||||
addi sp,sp,32
|
||||
tail free@plt
|
||||
.size destroyLinkedList, .-destroyLinkedList
|
||||
.ident "GCC: (Debian 12.2.0-13) 12.2.0"
|
||||
.section .note.GNU-stack,"",@progbits
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
mod quicksort;
|
||||
mod linkedlist;
|
||||
|
||||
pub use quicksort::*;
|
||||
pub use linkedlist::*;
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
// #[cfg(test)]
|
||||
pub mod tests {
|
||||
use compiler::{backend::*, middle::ir::instruction::binary_inst::Add};
|
||||
use var::{ArrVar, Str, Var};
|
||||
|
||||
#[test]
|
||||
pub fn quicksort_example() {
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let bgea1a2lbb0_17 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
|
||||
);
|
||||
entry.extend_insts(vec![addispsp_32, sdra24sp, sds016sp, sds18sp, sds20sp, bgea1a2lbb0_17]);
|
||||
let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
|
||||
let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
|
||||
let jlbb0_3 = Inst::Jmp(JmpInst::new("LBB0_3".into()));
|
||||
entry.extend_insts(vec![mvs2a2, mvs1a0, jlbb0_3]);
|
||||
|
||||
let mut lbb0_2 = Block::new("lbb0_2".into());
|
||||
let sllia2s02 = Inst::SLL(SllInst::new(REG_A2.into(), REG_S0.into(), (2).into()));
|
||||
let adda2a2s1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), REG_S1.into()));
|
||||
let swa00a2 = Inst::Sw(SwInst::new(REG_A0.into(), (0).into(), REG_A2.into()));
|
||||
let addia2s0_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_S0.into(), (-1).into()));
|
||||
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
|
||||
let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
|
||||
let addia1s01 = Inst::Add(AddInst::new(REG_A1.into(), REG_S0.into(), (1).into()));
|
||||
let bgea1s2lbb0_17 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into())
|
||||
);
|
||||
lbb0_2.extend_insts(
|
||||
vec![
|
||||
sllia2s02,
|
||||
adda2a2s1,
|
||||
swa00a2,
|
||||
addia2s0_1,
|
||||
mva0s1,
|
||||
callquicksort,
|
||||
addia1s01,
|
||||
bgea1s2lbb0_17,
|
||||
]
|
||||
);
|
||||
|
||||
let mut lbb0_3 = Block::new("LBB0_3".into());
|
||||
let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
|
||||
let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into()));
|
||||
let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
|
||||
let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
|
||||
let bgea1s2lbb0_2 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into())
|
||||
);
|
||||
lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, lwa00a0, mvs0a1, bgea1s2lbb0_2]);
|
||||
let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
|
||||
let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into()));
|
||||
let jlbb0_7 = Inst::Jmp(JmpInst::new("LBB0_7".into()));
|
||||
lbb0_3.extend_insts(vec![mvs0a1, mva2s2, jlbb0_7]);
|
||||
|
||||
let mut lbb0_5 = Block::new("LBB0_5".into());
|
||||
let sllis3s22 = Inst::SLL(SllInst::new(REG_S3.into(), REG_S2.into(), (2).into()));
|
||||
let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
|
||||
let swa40a3 = Inst::Sw(SwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
|
||||
let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
|
||||
lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, swa40a3, addia2a2_1]);
|
||||
|
||||
let mut llb0_6 = Block::new("LBB0_6".into());
|
||||
let bges0a2lbb0_2 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into())
|
||||
);
|
||||
llb0_6.extend_insts(vec![bges0a2lbb0_2]);
|
||||
|
||||
let mut lbb0_7 = Block::new("LBB0_7".into());
|
||||
let bges0a2lbb0_11 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into())
|
||||
);
|
||||
lbb0_7.extend_insts(vec![bges0a2lbb0_11]);
|
||||
let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
|
||||
let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
|
||||
let mva4a2 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A2.into()));
|
||||
lbb0_7.extend_insts(vec![sllia3a22, adda3a3s1, mva4a2]);
|
||||
|
||||
let mut lbb0_9 = Block::new("LBB0_9".into());
|
||||
let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
|
||||
let blta5a0lbb0_12 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into())
|
||||
);
|
||||
lbb0_9.extend_insts(vec![lwa50a3, blta5a0lbb0_12]);
|
||||
let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into()));
|
||||
let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
|
||||
let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into()));
|
||||
let blts0a4lbb0_9 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into())
|
||||
);
|
||||
lbb0_9.extend_insts(vec![addia4a4_1, addia2a2_1, addia3a3_4, blts0a4lbb0_9]);
|
||||
|
||||
let mut lbb0_11 = Block::new("LBB0_11".into());
|
||||
let bges0a2lbb0_6 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
|
||||
);
|
||||
let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into()));
|
||||
lbb0_11.extend_insts(vec![bges0a2lbb0_6, jlbb0_13]);
|
||||
|
||||
let mut lbb0_12 = Block::new("LBB0_12".into());
|
||||
let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
|
||||
let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
|
||||
let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
|
||||
let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
|
||||
let bges0a2lbb0_6 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
|
||||
);
|
||||
lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, swa50a3, addis0s01, bges0a2lbb0_6]);
|
||||
|
||||
let mut lbb0_13 = Block::new("LBB0_13".into());
|
||||
let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
|
||||
let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
|
||||
lbb0_13.extend_insts(vec![sllia3s02, adda3a3s1]);
|
||||
|
||||
let mut lbb0_14 = Block::new("LBB0_14".into());
|
||||
// lw a4, 0(a3)
|
||||
let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
|
||||
let bgea4a0lbb0_5 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into())
|
||||
);
|
||||
lbb0_14.extend_insts(vec![lwa40a3, bgea4a0lbb0_5]);
|
||||
// push_inst lw
|
||||
let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
|
||||
let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into()));
|
||||
let bnea2s0lbb0_14 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into())
|
||||
);
|
||||
lbb0_14.extend_insts(vec![addis0s01, addia3a34, bnea2s0lbb0_14]);
|
||||
let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into()));
|
||||
let jlbb0_2 = Inst::Jmp(JmpInst::new("LBB0_2".into()));
|
||||
lbb0_14.extend_insts(vec![mvs0a2, jlbb0_2]);
|
||||
|
||||
let mut lbb0_17 = Block::new("LBB0_17".into());
|
||||
let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
lbb0_17.extend_insts(vec![lia00, ldra24sp, lds016sp, lds18sp, lds20sp, addispsp32, ret]);
|
||||
|
||||
let mut quickSort = Func::new("QuickSort".into(), Vec::new(), entry);
|
||||
quickSort.push_bb(lbb0_2);
|
||||
quickSort.push_bb(lbb0_3);
|
||||
quickSort.push_bb(lbb0_5);
|
||||
quickSort.push_bb(llb0_6);
|
||||
quickSort.push_bb(lbb0_7);
|
||||
quickSort.push_bb(lbb0_9);
|
||||
quickSort.push_bb(lbb0_11);
|
||||
quickSort.push_bb(lbb0_12);
|
||||
quickSort.push_bb(lbb0_13);
|
||||
quickSort.push_bb(lbb0_14);
|
||||
quickSort.push_bb(lbb0_17);
|
||||
|
||||
// .LC0:
|
||||
// .string "%d\n"
|
||||
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let lia29 = Inst::Add(AddInst::new(REG_A2.into(), REG_ZERO.into(), (9).into()));
|
||||
let lia10 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (9).into()));
|
||||
// TODO lla a0 arr
|
||||
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
// lla s0 arr
|
||||
let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
|
||||
// lla s2 arr+40
|
||||
// lla s1 LC0 , lc0 is .string "%d\n"
|
||||
entry.extend_insts(
|
||||
vec![
|
||||
addispsp_32,
|
||||
lia29,
|
||||
lia10,
|
||||
/* lla a0, arr */ sds016sp,
|
||||
sds18sp,
|
||||
sds20sp,
|
||||
sdra24sp,
|
||||
/* lla s0 arr */
|
||||
callquicksort, /* lla s1 LC0 */
|
||||
/* lla s2, arr+40 */
|
||||
]
|
||||
);
|
||||
|
||||
let mut l35 = Block::new("L35".into());
|
||||
let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
|
||||
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
|
||||
let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into()));
|
||||
let callprintf = Inst::Call(CallInst::new("printf@plt".into()));
|
||||
let bnes0s2l35 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into())
|
||||
);
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
l35.extend_insts(
|
||||
vec![
|
||||
lwa10s0,
|
||||
mva0s1,
|
||||
addis0s04,
|
||||
callprintf,
|
||||
bnes0s2l35,
|
||||
ldra24sp,
|
||||
lds016sp,
|
||||
lds18sp,
|
||||
lds20sp,
|
||||
lia00,
|
||||
addispsp32,
|
||||
ret,
|
||||
]
|
||||
);
|
||||
let mut Main = Func::new("main".into(), Vec::new(), entry);
|
||||
Main.push_bb(l35);
|
||||
|
||||
// let lc0 = Var::Str { Str { name : "LC0", init : "%d\n", is_const : true } };
|
||||
let lc0 = Var::Str(Str {
|
||||
name: "LC0".into(),
|
||||
init: Some("%d\n".to_string()),
|
||||
is_const: true,
|
||||
});
|
||||
|
||||
let arr = Var::IntArr(ArrVar {
|
||||
name: "arr".to_string(),
|
||||
capacity: 10,
|
||||
init: vec![
|
||||
(0, 4),
|
||||
(1, 3),
|
||||
(2, 9),
|
||||
(3, 2),
|
||||
(4, 0),
|
||||
(5, 1),
|
||||
(6, 6),
|
||||
(7, 5),
|
||||
(8, 7),
|
||||
(9, 9),
|
||||
],
|
||||
is_const: false,
|
||||
});
|
||||
|
||||
let main_module = Module {
|
||||
name: "main".into(),
|
||||
global: vec![lc0, arr],
|
||||
funcs: vec![Main, quickSort],
|
||||
entry: Some("main".to_string()),
|
||||
};
|
||||
print!("{}", main_module.gen_asm());
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
mod ch2;
|
||||
|
||||
use std::{ fs::File, io::Write };
|
||||
|
||||
use compiler::backend::*;
|
||||
|
||||
fn main() {}
|
||||
Loading…
Reference in New Issue