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需要 lla 指令

This commit is contained in:
wangfiox 2024-06-11 15:39:35 +08:00
parent 96509a0252
commit c3214191ff
1 changed files with 96 additions and 61 deletions
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157
src/ch2/quicksort.rs
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@ -1,6 +1,7 @@
#[cfg(test)] // #[cfg(test)]
pub mod tests { pub mod tests {
use compiler::{ backend::*, middle::ir::instruction::binary_inst::Add }; use compiler::{ backend::*, middle::ir::instruction::binary_inst::Add };
use var::{ ArrVar, Str, Var };
#[test] #[test]
pub fn quicksort_example() { pub fn quicksort_example() {
@ -157,68 +158,102 @@ pub mod tests {
quickSort.push_bb(lbb0_14); quickSort.push_bb(lbb0_14);
quickSort.push_bb(lbb0_17); quickSort.push_bb(lbb0_17);
// main: # @main // .LC0:
// addi sp, sp, -80 // .string "%d\n"
// sd ra, 72(sp) # 8-byte Folded Spill
// sd s0, 64(sp) # 8-byte Folded Spill
// sd s1, 56(sp) # 8-byte Folded Spill
// sd s2, 48(sp) # 8-byte Folded Spill
let mut entry = Block::new("entry".into()); let mut entry = Block::new("entry".into());
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into())); let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
let lia29 = Inst::Add(AddInst::new(REG_A2.into(), REG_ZERO.into(), (9).into())); let lia29 = Inst::Add(AddInst::new(REG_A2.into(), REG_ZERO.into(), (9).into()));
let lia10 = Inst::Add(AddInst::new(REG_A1.into(), REG_ZERO.into(), (0).into())); let lia10 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (9).into()));
let sdra16sp = Inst::Sd(SdInst::new(REG_RA.into(), (72).into(), REG_SP.into())); // TODO lla a0 arr
let sds18sp = Inst::Sd(SdInst::new(REG_S0.into(), (64).into(), REG_SP.into())); let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
let sds10sp = Inst::Sd(SdInst::new(REG_S1.into(), (56).into(), REG_SP.into())); let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
let sds124sp = Inst::Sd(SdInst::new(REG_S2.into(), (48).into(), REG_SP.into())); let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
// # %bb.0: let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
// .Lpcrel_hi0: // lla s0 arr
// auipc s2, %pcrel_hi(n) let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
// li a0, 10 // lla s2 arr+40
// sw a0, %pcrel_lo(.Lpcrel_hi0)(s2) // lla s1 LC0 , lc0 is .string "%d\n"
// li a0, 4 entry.extend_insts(
// sw a0, 8(sp) vec![
// li a0, 3 addispsp_32,
// sw a0, 12(sp) lia29,
// li a0, 9 lia10,
// sw a0, 16(sp) /* lla a0, arr */ sds016sp,
// li a0, 2 sds18sp,
// sw a0, 20(sp) sds20sp,
// sw zero, 24(sp) sdra24sp,
// li a0, 1 /* lla s0 arr */
// sw a0, 28(sp) callquicksort /* lla s1 LC0 */
// li a0, 6 /* lla s2, arr+40 */
// sw a0, 32(sp) ]
// li a0, 5 );
// sw a0, 36(sp)
// li a0, 7 let mut l35 = Block::new("L35".into());
// sw a0, 40(sp) let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
// li a0, 8 let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
// sw a0, 44(sp) let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into()));
// addi a0, sp, 8 let callprintf = Inst::Call(CallInst::new("printf@plt".into()));
// li a2, 9 let bnes0s2l35 = Inst::Branch(
// addi s1, sp, 8 BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into())
// li a1, 0 );
// call QuickSort let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
// li s0, 0 let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
// .LBB1_1: # =>This Inner Loop Header: Depth=1 let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
// lw a0, 0(s1) let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
// call putint@plt let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
// li a0, 10 let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
// call putch@plt let ret = Inst::Ret;
// li a0, 10 l35.extend_insts(
// call putch@plt vec![
// lw a0, %pcrel_lo(.Lpcrel_hi0)(s2) lwa10s0,
// addi s0, s0, 1 mva0s1,
// addi s1, s1, 4 addis0s04,
// blt s0, a0, .LBB1_1 callprintf,
// # %bb.2: bnes0s2l35,
// li a0, 0 ldra24sp,
// ld ra, 72(sp) # 8-byte Folded Reload lds016sp,
// ld s0, 64(sp) # 8-byte Folded Reload lds18sp,
// ld s1, 56(sp) # 8-byte Folded Reload lds20sp,
// ld s2, 48(sp) # 8-byte Folded Reload lia00,
// addi sp, sp, 80 addispsp32,
// ret ret
]
);
let mut Main = Func::new("main".into(), Vec::new(), entry);
Main.push_bb(l35);
// let lc0 = Var::Str { Str { name : "LC0", init : "%d\n", is_const : true } };
let lc0 = Var::Str(Str {
name: "LC0".into(),
init: Some("%d\n".to_string()),
is_const: true,
});
let arr = Var::IntArr(ArrVar {
name: "arr".to_string(),
capacity: 10,
init: vec![
(0, 4),
(1, 3),
(2, 9),
(3, 2),
(4, 0),
(5, 1),
(6, 6),
(7, 5),
(8, 7),
(9, 9)
],
is_const: false,
});
let main_module = Module {
name: "main".into(),
global: vec![lc0, arr],
funcs: vec![Main, quickSort],
entry: Some("main".to_string()),
};
print!("{}", main_module.gen_asm());
} }
} }