需要 lla 指令
This commit is contained in:
wangfiox
parent
96509a0252
commit
c3214191ff
|
|
@ -1,6 +1,7 @@
|
|||
#[cfg(test)]
|
||||
// #[cfg(test)]
|
||||
pub mod tests {
|
||||
use compiler::{ backend::*, middle::ir::instruction::binary_inst::Add };
|
||||
use var::{ ArrVar, Str, Var };
|
||||
|
||||
#[test]
|
||||
pub fn quicksort_example() {
|
||||
|
|
@ -157,68 +158,102 @@ pub mod tests {
|
|||
quickSort.push_bb(lbb0_14);
|
||||
quickSort.push_bb(lbb0_17);
|
||||
|
||||
// main: # @main
|
||||
// addi sp, sp, -80
|
||||
// sd ra, 72(sp) # 8-byte Folded Spill
|
||||
// sd s0, 64(sp) # 8-byte Folded Spill
|
||||
// sd s1, 56(sp) # 8-byte Folded Spill
|
||||
// sd s2, 48(sp) # 8-byte Folded Spill
|
||||
// .LC0:
|
||||
// .string "%d\n"
|
||||
|
||||
let mut entry = Block::new("entry".into());
|
||||
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
|
||||
let lia29 = Inst::Add(AddInst::new(REG_A2.into(), REG_ZERO.into(), (9).into()));
|
||||
let lia10 = Inst::Add(AddInst::new(REG_A1.into(), REG_ZERO.into(), (0).into()));
|
||||
let sdra16sp = Inst::Sd(SdInst::new(REG_RA.into(), (72).into(), REG_SP.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S0.into(), (64).into(), REG_SP.into()));
|
||||
let sds10sp = Inst::Sd(SdInst::new(REG_S1.into(), (56).into(), REG_SP.into()));
|
||||
let sds124sp = Inst::Sd(SdInst::new(REG_S2.into(), (48).into(), REG_SP.into()));
|
||||
// # %bb.0:
|
||||
// .Lpcrel_hi0:
|
||||
// auipc s2, %pcrel_hi(n)
|
||||
// li a0, 10
|
||||
// sw a0, %pcrel_lo(.Lpcrel_hi0)(s2)
|
||||
// li a0, 4
|
||||
// sw a0, 8(sp)
|
||||
// li a0, 3
|
||||
// sw a0, 12(sp)
|
||||
// li a0, 9
|
||||
// sw a0, 16(sp)
|
||||
// li a0, 2
|
||||
// sw a0, 20(sp)
|
||||
// sw zero, 24(sp)
|
||||
// li a0, 1
|
||||
// sw a0, 28(sp)
|
||||
// li a0, 6
|
||||
// sw a0, 32(sp)
|
||||
// li a0, 5
|
||||
// sw a0, 36(sp)
|
||||
// li a0, 7
|
||||
// sw a0, 40(sp)
|
||||
// li a0, 8
|
||||
// sw a0, 44(sp)
|
||||
// addi a0, sp, 8
|
||||
// li a2, 9
|
||||
// addi s1, sp, 8
|
||||
// li a1, 0
|
||||
// call QuickSort
|
||||
// li s0, 0
|
||||
// .LBB1_1: # =>This Inner Loop Header: Depth=1
|
||||
// lw a0, 0(s1)
|
||||
// call putint@plt
|
||||
// li a0, 10
|
||||
// call putch@plt
|
||||
// li a0, 10
|
||||
// call putch@plt
|
||||
// lw a0, %pcrel_lo(.Lpcrel_hi0)(s2)
|
||||
// addi s0, s0, 1
|
||||
// addi s1, s1, 4
|
||||
// blt s0, a0, .LBB1_1
|
||||
// # %bb.2:
|
||||
// li a0, 0
|
||||
// ld ra, 72(sp) # 8-byte Folded Reload
|
||||
// ld s0, 64(sp) # 8-byte Folded Reload
|
||||
// ld s1, 56(sp) # 8-byte Folded Reload
|
||||
// ld s2, 48(sp) # 8-byte Folded Reload
|
||||
// addi sp, sp, 80
|
||||
// ret
|
||||
let lia10 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (9).into()));
|
||||
// TODO lla a0 arr
|
||||
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
// lla s0 arr
|
||||
let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
|
||||
// lla s2 arr+40
|
||||
// lla s1 LC0 , lc0 is .string "%d\n"
|
||||
entry.extend_insts(
|
||||
vec![
|
||||
addispsp_32,
|
||||
lia29,
|
||||
lia10,
|
||||
/* lla a0, arr */ sds016sp,
|
||||
sds18sp,
|
||||
sds20sp,
|
||||
sdra24sp,
|
||||
/* lla s0 arr */
|
||||
callquicksort /* lla s1 LC0 */
|
||||
/* lla s2, arr+40 */
|
||||
]
|
||||
);
|
||||
|
||||
let mut l35 = Block::new("L35".into());
|
||||
let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
|
||||
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
|
||||
let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into()));
|
||||
let callprintf = Inst::Call(CallInst::new("printf@plt".into()));
|
||||
let bnes0s2l35 = Inst::Branch(
|
||||
BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into())
|
||||
);
|
||||
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
|
||||
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
|
||||
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
|
||||
let lds20sp = Inst::Ld(LdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
|
||||
let lia00 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (0).into()));
|
||||
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
|
||||
let ret = Inst::Ret;
|
||||
l35.extend_insts(
|
||||
vec![
|
||||
lwa10s0,
|
||||
mva0s1,
|
||||
addis0s04,
|
||||
callprintf,
|
||||
bnes0s2l35,
|
||||
ldra24sp,
|
||||
lds016sp,
|
||||
lds18sp,
|
||||
lds20sp,
|
||||
lia00,
|
||||
addispsp32,
|
||||
ret
|
||||
]
|
||||
);
|
||||
let mut Main = Func::new("main".into(), Vec::new(), entry);
|
||||
Main.push_bb(l35);
|
||||
|
||||
// let lc0 = Var::Str { Str { name : "LC0", init : "%d\n", is_const : true } };
|
||||
let lc0 = Var::Str(Str {
|
||||
name: "LC0".into(),
|
||||
init: Some("%d\n".to_string()),
|
||||
is_const: true,
|
||||
});
|
||||
|
||||
let arr = Var::IntArr(ArrVar {
|
||||
name: "arr".to_string(),
|
||||
capacity: 10,
|
||||
init: vec![
|
||||
(0, 4),
|
||||
(1, 3),
|
||||
(2, 9),
|
||||
(3, 2),
|
||||
(4, 0),
|
||||
(5, 1),
|
||||
(6, 6),
|
||||
(7, 5),
|
||||
(8, 7),
|
||||
(9, 9)
|
||||
],
|
||||
is_const: false,
|
||||
});
|
||||
|
||||
let main_module = Module {
|
||||
name: "main".into(),
|
||||
global: vec![lc0, arr],
|
||||
funcs: vec![Main, quickSort],
|
||||
entry: Some("main".to_string()),
|
||||
};
|
||||
print!("{}", main_module.gen_asm());
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue