wangfiox
/
backend_module
1
0
Fork 0
Code Issues 1 Pull Requests Packages Projects Releases Wiki Activity

modified: src/ch2/linkedlist.rs

This commit is contained in:
wangfiox 2024-06-12 13:53:20 +08:00
parent e394b1a3de
commit e20c34d2e9
1 changed files with 80 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

85
src/ch2/linkedlist.rs
View File

@ -1,7 +1,9 @@
pub mod tests {
use compiler::backend::{AddInst, Block, BranchInst, BranchOp, CallInst, Inst, JmpInst, LdInst, MvInst, REG_A0, REG_A1, REG_A2, REG_RA, REG_S0, REG_S1, REG_S2, REG_SP, REG_ZERO, SdInst};
use compiler::backend::Inst::{Call, Jmp};
use compiler::frontend::Decl::Func;
use compiler::backend::{
AddInst, Block, BranchInst, BranchOp, CallInst, Func, Inst, JmpInst, LdInst, MvInst,
SdInst, REG_A0, REG_A1, REG_A2, REG_A3, REG_RA, REG_S0, REG_S1, REG_S2, REG_SP, REG_ZERO,
};
#[test]
pub fn linked() {
@ -12,14 +14,37 @@ pub mod tests {
let sdra8sp = Inst::Sd(SdInst::new(REG_RA.into(), (8).into(), REG_SP.into()));
let sds00sp = Inst::Sd(SdInst::new(REG_S0.into(), (0).into(), REG_SP.into()));
let callmalloc1 = Inst::Call(CallInst::new("malloc@plt".into()));
let beqa0zerol2 = Inst::Branch(BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L2".into()));
let beqa0zerol2 = Inst::Branch(BranchInst::new(
BranchOp::Beq,
REG_A0.into(),
REG_ZERO.into(),
"L2".into(),
));
let mvs0a0 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A0.into()));
let lia016 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (16).into()));
let callmalloc2 = Inst::Call(CallInst::new("malloc@plt".into()));
let sda00s0 = Inst::Sd(SdInst::new(REG_A0.into(), (0).into(), REG_S0.into()));
let beqa0zerol3 = Inst::Branch(BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L3".into()));
let beqa0zerol3 = Inst::Branch(BranchInst::new(
BranchOp::Beq,
REG_A0.into(),
REG_ZERO.into(),
"L3".into(),
));
let sdzero8a0 = Inst::Sd(SdInst::new(REG_ZERO.into(), (8).into(), REG_A0.into()));
entry.extend_insts(vec![addispsp_16, lia08, sdra8sp, sds00sp, callmalloc1, beqa0zerol2, mvs0a0, lia016, callmalloc2, sda00s0, beqa0zerol3, sdzero8a0]);
entry.extend_insts(vec![
addispsp_16,
lia08,
sdra8sp,
sds00sp,
callmalloc1,
beqa0zerol2,
mvs0a0,
lia016,
callmalloc2,
sda00s0,
beqa0zerol3,
sdzero8a0,
]);
// L1
let mut l1 = Block::new("L1".into());
let ldra8sp = Inst::Ld(LdInst::new(REG_RA.into(), (8).into(), REG_SP.into()));
@ -37,9 +62,57 @@ pub mod tests {
let jl1 = Inst::Jmp(JmpInst::new("L1".into()));
l2.extend_insts(vec![lis00, jl1]);
let createLinkedList = Func::new("createLinkedList".into(), Vec::new(), entry);
let mut createLinkedList = Func::new("createLinkedList".into(), Vec::new(), entry);
createLinkedList.push_bb(l1);
createLinkedList.push_bb(l2);
createLinkedList.push_bb(l3);
let mut entry = Block::new("entry".into());
let addispsp_32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-32).into()));
let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
let lds00a0 = Inst::Ld(LdInst::new(REG_SP.into(), (0).into(), REG_A0.into()));
let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
let beqs0zerol31 = Inst::Branch(BranchInst::new(
BranchOp::Beq,
REG_S0.into(),
REG_ZERO.into(),
"L31".into(),
));
entry.extend_insts(vec![
addispsp_32,
sds016sp,
lds00a0,
sds18sp,
sdra24sp,
mvs1a0,
beqs0zerol31,
]);
let mut l32 = Block::new("L32".into());
let mva0s0 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S0.into()));
let lds08s0 = Inst::Ld(LdInst::new(REG_S0.into(), (8).into(), REG_S0.into()));
let callfree = Inst::Call(CallInst::new("free@plt".into()));
let bnes0zerol32 = Inst::Branch(BranchInst::new(
BranchOp::Bne,
REG_S0.into(),
REG_ZERO.into(),
"L32".into(),
));
l32.extend_insts(vec![mva0s0, lds08s0, callfree, bnes0zerol32]);
let mut l31 = Block::new("L32".into());
let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
let addispsp32 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (32).into()));
//let tailfree = Inst::
l31.extend_insts(vec![lds016sp, ldra24sp, mva0s1, lds18sp, addispsp32]);
let mut destroyLinkedList = Func::new("destroyLinkedList".into(), Vec::new(), entry);
destroyLinkedList.push_bb(l32);
destroyLinkedList.push_bb(l31);
}
}