modified: shell.nix

.vscode/settings.json

@@ -0,0 +1,3 @@
+{
+  "nixEnvSelector.nixFile": "${workspaceFolder}/shell.nix"
+}

hitc

@@ -1 +1 @@
-Subproject commit c5a2f47e6a5817b47ac5670a8c22acc76b0662b4
+Subproject commit 52893ac4409b6879e5d91126493c7d5c88038797

shell.nix

@@ -0,0 +1,17 @@
+{ pkgs ? import <nixpkgs> { } }:
+pkgs.mkShell {
+  nativeBuildInputs = with pkgs; [ rustc cargo gcc rustfmt clippy ];
+
+  # Certain Rust tools won't work without this
+  # This can also be fixed by using oxalica/rust-overlay and specifying the rust-src extension
+  # See https://discourse.nixos.org/t/rust-src-not-found-and-other-misadventures-of-developing-rust-on-nixos/11570/3?u=samuela. for more details.
+  RUST_SRC_PATH = "${pkgs.rust.packages.stable.rustPlatform.rustLibSrc}";
+  shellHook = ''
+    # Set fish as the default shell
+    SHELL=${pkgs.fish}/bin/fish
+
+    # Configure git
+    git config --global user.name "wangfiox"
+    git config --global user.email "wangfiox@gmail.com"
+  '';
+}

src/ch2/linkedlist.rs

@@ -1,34 +1,5 @@
 pub mod tests {
-    use compiler::backend::Inst::{ Call, Jmp };
+    use compiler::backend::*;
-    use compiler::backend::{
-        AddInst,
-        Block,
-        BranchInst,
-        BranchOp,
-        CallInst,
-        Func,
-        Inst,
-        JmpInst,
-        LdInst,
-        LwInst,
-        Module,
-        MvInst,
-        SdInst,
-        SwInst,
-        REG_A0,
-        REG_A1,
-        REG_A2,
-        REG_A3,
-        REG_A4,
-        REG_A5,
-        REG_RA,
-        REG_S0,
-        REG_S1,
-        REG_S2,
-        REG_SP,
-        REG_ZERO,
-    };
-    use compiler::middle::ir::InstPtr;
 
     #[test]
     pub fn linked() {
@@ -40,16 +11,12 @@ pub mod tests {
         let sdra8sp = Inst::Sd(SdInst::new(REG_RA.into(), (8).into(), REG_SP.into()));
         let sds00sp = Inst::Sd(SdInst::new(REG_S0.into(), (0).into(), REG_SP.into()));
         let callmalloc1 = Inst::Call(CallInst::new("malloc@plt".into()));
-        let beqa0zerol2 = Inst::Branch(
+        let beqa0zerol2 = Inst::Beq(BeqInst::new(REG_A0.into(), REG_ZERO.into(), "L2".into()));
-            BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L2".into())
-        );
         let mvs0a0 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A0.into()));
         let lia016 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (16).into()));
         let callmalloc2 = Inst::Call(CallInst::new("malloc@plt".into()));
         let sda00s0 = Inst::Sd(SdInst::new(REG_A0.into(), (0).into(), REG_S0.into()));
-        let beqa0zerol3 = Inst::Branch(
+        let beqa0zerol3 = Inst::Beq(BeqInst::new(REG_A0.into(), REG_ZERO.into(), "L3".into()));
-            BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L3".into())
-        );
         let sdzero8a0 = Inst::Sd(SdInst::new(REG_ZERO.into(), (8).into(), REG_A0.into()));
         entry.extend_insts(
             vec![
@@ -98,9 +65,7 @@ pub mod tests {
         let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
         let sdra24sp = Inst::Sd(SdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
         let mvs1a0 = Inst::Mv(MvInst::new(REG_S1.into(), REG_A0.into()));
-        let beqs0zerol31 = Inst::Branch(
+        let beqs0zerol31 = Inst::Beq(BeqInst::new(REG_S0.into(), REG_ZERO.into(), "L31".into()));
-            BranchInst::new(BranchOp::Beq, REG_S0.into(), REG_ZERO.into(), "L31".into())
-        );
         entry.extend_insts(
             vec![addispsp_32, sds016sp, lds00a0, sds18sp, sdra24sp, mvs1a0, beqs0zerol31]
         );
@@ -109,9 +74,7 @@ pub mod tests {
         let mva0s0 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S0.into()));
         let lds08s0 = Inst::Ld(LdInst::new(REG_S0.into(), (8).into(), REG_S0.into()));
         let callfree = Inst::Call(CallInst::new("free@plt".into()));
-        let bnes0zerol32 = Inst::Branch(
+        let bnes0zerol32 = Inst::Bne(BneInst::new(REG_S0.into(), REG_ZERO.into(), "L32".into()));
-            BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_ZERO.into(), "L32".into())
-        );
         l32.extend_insts(vec![mva0s0, lds08s0, callfree, bnes0zerol32]);
 
         let mut l31 = Block::new("L32".into());
@@ -132,9 +95,7 @@ pub mod tests {
         let lda50a0 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
         let lda08a5 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A5.into()));
         //	bne	a0,zero,.L22
-        let bnea0zerol22 = Inst::Branch(
+        let bnea0zerol22 = Inst::Bne(BneInst::new(REG_A0.into(), REG_ZERO.into(), "L22".into()));
-            BranchInst::new(BranchOp::Bne, REG_A0.into(), REG_ZERO.into(), "L22".into())
-        );
         let jl29 = Inst::Jmp(JmpInst::new("L29".into()));
         entry.extend_insts(vec![lda50a0, lda08a5, bnea0zerol22, jl29]);
 
@@ -142,17 +103,13 @@ pub mod tests {
         //.L24:
         let mut l24 = Block::new("L24".into());
         let lda08a0 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A0.into()));
-        let beqa0zerol21 = Inst::Branch(
+        let beqa0zerol21 = Inst::Beq(BeqInst::new(REG_A0.into(), REG_ZERO.into(), "L21".into()));
-            BranchInst::new(BranchOp::Beq, REG_A0.into(), REG_ZERO.into(), "L21".into())
-        );
         l24.extend_insts(vec![lda08a0, beqa0zerol21]);
 
         let mut l22 = Block::new("L22".into());
-        let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
+        // let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
-        let bnea5a1l24 = Inst::Branch(
+        let bnea5a1l24 = Inst::Bne(BneInst::new(REG_A5.into(), REG_A1.into(), "L24".into()));
-            BranchInst::new(BranchOp::Bne, REG_A5.into(), REG_A1.into(), "L24".into())
+        l22.extend_insts(vec![/* lwa50a0, */ bnea5a1l24]);
-        );
-        l22.extend_insts(vec![lwa50a0, bnea5a1l24]);
 
         let mut l21 = Block::new("L21".into());
         let ret = Inst::Ret;
@@ -178,19 +135,15 @@ pub mod tests {
 
         //.L20:
         let mut l20 = Block::new("L20".into());
-        let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
+        // let lwa50a0 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A0.into()));
-        let beqa5a1L19 = Inst::Branch(
+        let beqa5a1L19 = Inst::Beq(BeqInst::new(REG_A5.into(), REG_A1.into(), "L19".into()));
-            BranchInst::new(BranchOp::Beq, REG_A5.into(), REG_A1.into(), "L19".into())
+        l20.extend_insts(vec![/* lwa50a0, */ beqa5a1L19]);
-        );
-        l20.extend_insts(vec![lwa50a0, beqa5a1L19]);
 
         //.L16:
         let mut l16 = Block::new("L16".into());
         let mva4a0 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A0.into()));
         let lda08a0 = Inst::Ld(LdInst::new(REG_A0.into(), (8).into(), REG_A0.into()));
-        let bnea0zeroL20 = Inst::Branch(
+        let bnea0zeroL20 = Inst::Bne(BneInst::new(REG_A0.into(), REG_ZERO.into(), "L20".into()));
-            BranchInst::new(BranchOp::Bne, REG_A0.into(), REG_ZERO.into(), "L20".into())
-        );
         let ret = Inst::Ret;
         l16.extend_insts(vec![mva4a0, lda08a0, bnea0zeroL20, ret]);
 
@@ -217,7 +170,7 @@ pub mod tests {
         let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
         let callmalloc = Inst::Call(CallInst::new("malloc@plt".into()));
         let lda50s1 = Inst::Ld(LdInst::new(REG_A5.into(), (0).into(), REG_S1.into()));
-        let sws00a0 = Inst::Sw(SwInst::new(REG_S0.into(), (0).into(), REG_A0.into()));
+        // let sws00a0 = Inst::S(SwInst::new(REG_S0.into(), (0).into(), REG_A0.into()));
         let sdzero8a0 = Inst::Sd(SdInst::new(REG_ZERO.into(), (8).into(), REG_A0.into()));
         entry.extend_insts(
             vec![
@@ -230,7 +183,7 @@ pub mod tests {
                 mvs0a1,
                 callmalloc,
                 lda50s1,
-                sws00a0,
+                // sws00a0,
                 sdzero8a0
             ]
         );
@@ -238,9 +191,7 @@ pub mod tests {
         let mut l11 = Block::new("L11".into());
         let mva4a5 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A5.into()));
         let lda58a5 = Inst::Ld(LdInst::new(REG_A5.into(), (8).into(), REG_A5.into()));
-        let bnea5zeroL11 = Inst::Branch(
+        let bnea5zeroL11 = Inst::Bne(BneInst::new(REG_A5.into(), REG_ZERO.into(), "L11".into()));
-            BranchInst::new(BranchOp::Bne, REG_A5.into(), REG_ZERO.into(), "L11".into())
-        );
         let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
         let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
         let sds08sp = Inst::Sd(SdInst::new(REG_S0.into(), (8).into(), REG_A4.into()));

src/ch2/quicksort.rs

@@ -11,8 +11,8 @@ pub mod tests {
         let sds016sp = Inst::Sd(SdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
         let sds18sp = Inst::Sd(SdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
         let sds20sp = Inst::Sd(SdInst::new(REG_S2.into(), (0).into(), REG_SP.into()));
-        let bgea1a2lbb0_17 = Inst::Branch(
+        let bgea1a2lbb0_17 = Inst::Bge(
-            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_A2.into(), "LBB0_17".into())
+            BgeInst::new(REG_A1.into(), REG_A2.into(), "LBB0_17".into())
         );
         entry.extend_insts(vec![addispsp_32, sdra24sp, sds016sp, sds18sp, sds20sp, bgea1a2lbb0_17]);
         let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
@@ -21,21 +21,21 @@ pub mod tests {
         entry.extend_insts(vec![mvs2a2, mvs1a0, jlbb0_3]);
 
         let mut lbb0_2 = Block::new("lbb0_2".into());
-        let sllia2s02 = Inst::SLL(SllInst::new(REG_A2.into(), REG_S0.into(), (2).into()));
+        let sllia2s02 = Inst::Sll(SllInst::new(REG_A2.into(), REG_S0.into(), (2).into()));
         let adda2a2s1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), REG_S1.into()));
-        let swa00a2 = Inst::Sw(SwInst::new(REG_A0.into(), (0).into(), REG_A2.into()));
+        // let swa00a2 = Inst::Sw(SwInst::new(REG_A0.into(), (0).into(), REG_A2.into()));
         let addia2s0_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_S0.into(), (-1).into()));
         let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
         let callquicksort = Inst::Call(CallInst::new("QuickSort".into()));
         let addia1s01 = Inst::Add(AddInst::new(REG_A1.into(), REG_S0.into(), (1).into()));
-        let bgea1s2lbb0_17 = Inst::Branch(
+        let bgea1s2lbb0_17 = Inst::Bge(
-            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_17".into())
+            BgeInst::new(REG_A1.into(), REG_S2.into(), "LBB0_17".into())
         );
         lbb0_2.extend_insts(
             vec![
                 sllia2s02,
                 adda2a2s1,
-                swa00a2,
+                // swa00a2,
                 addia2s0_1,
                 mva0s1,
                 callquicksort,
@@ -45,89 +45,77 @@ pub mod tests {
         );
 
         let mut lbb0_3 = Block::new("LBB0_3".into());
-        let sllia0a12 = Inst::SLL(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
+        let sllia0a12 = Inst::Sll(SllInst::new(REG_A0.into(), REG_A1.into(), (2).into()));
         let adda0a0s1 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), REG_S1.into()));
-        let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
+        // let lwa00a0 = Inst::Lw(LwInst::new(REG_A0.into(), (0).into(), REG_A0.into()));
         let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
-        let bgea1s2lbb0_2 = Inst::Branch(
+        let bgea1s2lbb0_2 = Inst::Bge(BgeInst::new(REG_A1.into(), REG_S2.into(), "LBB0_2".into()));
-            BranchInst::new(BranchOp::Bge, REG_A1.into(), REG_S2.into(), "LBB0_2".into())
+        lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, /* lwa00a0, */ mvs0a1, bgea1s2lbb0_2]);
-        );
-        lbb0_3.extend_insts(vec![sllia0a12, adda0a0s1, lwa00a0, mvs0a1, bgea1s2lbb0_2]);
         let mvs0a1 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A1.into()));
         let mva2s2 = Inst::Mv(MvInst::new(REG_A2.into(), REG_S2.into()));
         let jlbb0_7 = Inst::Jmp(JmpInst::new("LBB0_7".into()));
         lbb0_3.extend_insts(vec![mvs0a1, mva2s2, jlbb0_7]);
 
         let mut lbb0_5 = Block::new("LBB0_5".into());
-        let sllis3s22 = Inst::SLL(SllInst::new(REG_S3.into(), REG_S2.into(), (2).into()));
+        let sllis3s22 = Inst::Sll(SllInst::new(REG_S3.into(), REG_S2.into(), (2).into()));
         let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
-        let swa40a3 = Inst::Sw(SwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
+        // let swa40a3 = Inst::Sw(SwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
         let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
-        lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, swa40a3, addia2a2_1]);
+        lbb0_5.extend_insts(vec![sllis3s22, adda3a3s1, /* swa40a3, */ addia2a2_1]);
 
         let mut llb0_6 = Block::new("LBB0_6".into());
-        let bges0a2lbb0_2 = Inst::Branch(
+        let bges0a2lbb0_2 = Inst::Bge(BgeInst::new(REG_S0.into(), REG_A2.into(), "LBB0_2".into()));
-            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_2".into())
-        );
         llb0_6.extend_insts(vec![bges0a2lbb0_2]);
 
         let mut lbb0_7 = Block::new("LBB0_7".into());
-        let bges0a2lbb0_11 = Inst::Branch(
+        let bges0a2lbb0_11 = Inst::Bge(
-            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_11".into())
+            BgeInst::new(REG_S0.into(), REG_A2.into(), "LBB0_11".into())
         );
         lbb0_7.extend_insts(vec![bges0a2lbb0_11]);
-        let sllia3a22 = Inst::SLL(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
+        let sllia3a22 = Inst::Sll(SllInst::new(REG_A3.into(), REG_A2.into(), (2).into()));
         let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
         let mva4a2 = Inst::Mv(MvInst::new(REG_A4.into(), REG_A2.into()));
         lbb0_7.extend_insts(vec![sllia3a22, adda3a3s1, mva4a2]);
 
         let mut lbb0_9 = Block::new("LBB0_9".into());
-        let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
+        // let lwa50a3 = Inst::Lw(LwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
-        let blta5a0lbb0_12 = Inst::Branch(
+        let blta5a0lbb0_12 = Inst::Blt(
-            BranchInst::new(BranchOp::Blt, REG_A5.into(), REG_A0.into(), "LBB0_12".into())
+            BltInst::new(REG_A5.into(), REG_A0.into(), "LBB0_12".into())
         );
-        lbb0_9.extend_insts(vec![lwa50a3, blta5a0lbb0_12]);
+        lbb0_9.extend_insts(vec![/* lwa50a3, */ blta5a0lbb0_12]);
         let addia4a4_1 = Inst::Add(AddInst::new(REG_A4.into(), REG_A4.into(), (-1).into()));
         let addia2a2_1 = Inst::Add(AddInst::new(REG_A2.into(), REG_A2.into(), (-1).into()));
         let addia3a3_4 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (-4).into()));
-        let blts0a4lbb0_9 = Inst::Branch(
+        let blts0a4lbb0_9 = Inst::Blt(BltInst::new(REG_S0.into(), REG_A4.into(), "LBB0_9".into()));
-            BranchInst::new(BranchOp::Blt, REG_S0.into(), REG_A4.into(), "LBB0_9".into())
-        );
         lbb0_9.extend_insts(vec![addia4a4_1, addia2a2_1, addia3a3_4, blts0a4lbb0_9]);
 
         let mut lbb0_11 = Block::new("LBB0_11".into());
-        let bges0a2lbb0_6 = Inst::Branch(
+        let bges0a2lbb0_6 = Inst::Bge(BgeInst::new(REG_S0.into(), REG_A2.into(), "LBB0_6".into()));
-            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
-        );
         let jlbb0_13 = Inst::Jmp(JmpInst::new("LBB0_13".into()));
         lbb0_11.extend_insts(vec![bges0a2lbb0_6, jlbb0_13]);
 
         let mut lbb0_12 = Block::new("LBB0_12".into());
-        let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
+        let sllia3s02 = Inst::Sll(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
         let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
-        let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
+        // let swa50a3 = Inst::Sw(SwInst::new(REG_A5.into(), (0).into(), REG_A3.into()));
         let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
-        let bges0a2lbb0_6 = Inst::Branch(
+        let bges0a2lbb0_6 = Inst::Bge(BgeInst::new(REG_S0.into(), REG_A2.into(), "LBB0_6".into()));
-            BranchInst::new(BranchOp::Bge, REG_S0.into(), REG_A2.into(), "LBB0_6".into())
+        lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, /* swa50a3, */ addis0s01, bges0a2lbb0_6]);
-        );
-        lbb0_12.extend_insts(vec![sllia3s02, adda3a3s1, swa50a3, addis0s01, bges0a2lbb0_6]);
 
         let mut lbb0_13 = Block::new("LBB0_13".into());
-        let sllia3s02 = Inst::SLL(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
+        let sllia3s02 = Inst::Sll(SllInst::new(REG_A3.into(), REG_S0.into(), (2).into()));
         let adda3a3s1 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), REG_S1.into()));
         lbb0_13.extend_insts(vec![sllia3s02, adda3a3s1]);
 
         let mut lbb0_14 = Block::new("LBB0_14".into());
-        let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
+        // let lwa40a3 = Inst::Lw(LwInst::new(REG_A4.into(), (0).into(), REG_A3.into()));
-        let bgea4a0lbb0_5 = Inst::Branch(
+        let bgea4a0lbb0_5 = Inst::Bge(BgeInst::new(REG_A4.into(), REG_A0.into(), "LBB0_5".into()));
-            BranchInst::new(BranchOp::Bge, REG_A4.into(), REG_A0.into(), "LBB0_5".into())
+        lbb0_14.extend_insts(vec![/* lwa40a3, */ bgea4a0lbb0_5]);
-        );
-        lbb0_14.extend_insts(vec![lwa40a3, bgea4a0lbb0_5]);
         // push_inst lw
         let addis0s01 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (1).into()));
         let addia3a34 = Inst::Add(AddInst::new(REG_A3.into(), REG_A3.into(), (4).into()));
-        let bnea2s0lbb0_14 = Inst::Branch(
+        let bnea2s0lbb0_14 = Inst::Bne(
-            BranchInst::new(BranchOp::Bne, REG_A2.into(), REG_S0.into(), "LBB0_14".into())
+            BneInst::new(REG_A2.into(), REG_S0.into(), "LBB0_14".into())
         );
         lbb0_14.extend_insts(vec![addis0s01, addia3a34, bnea2s0lbb0_14]);
         let mvs0a2 = Inst::Mv(MvInst::new(REG_S0.into(), REG_A2.into()));
@@ -192,13 +180,11 @@ pub mod tests {
         );
 
         let mut l35 = Block::new("L35".into());
-        let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
+        // let lwa10s0 = Inst::Lw(LwInst::new(REG_A1.into(), (0).into(), REG_S0.into()));
         let mva0s1 = Inst::Mv(MvInst::new(REG_A0.into(), REG_S1.into()));
         let addis0s04 = Inst::Add(AddInst::new(REG_S0.into(), REG_S0.into(), (4).into()));
         let callprintf = Inst::Call(CallInst::new("printf@plt".into()));
-        let bnes0s2l35 = Inst::Branch(
+        let bnes0s2l35 = Inst::Bne(BneInst::new(REG_S0.into(), REG_S2.into(), "L35".into()));
-            BranchInst::new(BranchOp::Bne, REG_S0.into(), REG_S2.into(), "L35".into())
-        );
         let ldra24sp = Inst::Ld(LdInst::new(REG_RA.into(), (24).into(), REG_SP.into()));
         let lds016sp = Inst::Ld(LdInst::new(REG_S0.into(), (16).into(), REG_SP.into()));
         let lds18sp = Inst::Ld(LdInst::new(REG_S1.into(), (8).into(), REG_SP.into()));
@@ -208,7 +194,7 @@ pub mod tests {
         let ret = Inst::Ret;
         l35.extend_insts(
             vec![
-                lwa10s0,
+                // lwa10s0,
                 mva0s1,
                 addis0s04,
                 callprintf,

src/ch3/FuncPoint.rs

@@ -25,9 +25,7 @@ mod tests {
         /* ---------- ---------- sort ---------- ---------- */
         let mut entry = Block::new("entry".into());
         let lia51 = Inst::Add(AddInst::new(REG_A5.into(), REG_ZERO.into(), (1).into()));
-        let blea1a5L20 = Inst::Branch(
+        let blea1a5L20 = Inst::Ble(BleInst::new(REG_A1.into(), REG_A5.into(), "L20".into()));
-            BranchInst::new(BranchOp::Ble, REG_A1.into(), REG_A5.into(), "L20".into())
-        );
         let addispsp_64 = Inst::Add(AddInst::new(REG_SP.into(), REG_SP.into(), (-64).into()));
         let sds232sp = Inst::Sd(SdInst::new(REG_S2.into(), (32).into(), REG_SP.into()));
         let sds324sp = Inst::Sd(SdInst::new(REG_S3.into(), (24).into(), REG_SP.into()));
@@ -39,11 +37,36 @@ mod tests {
         let sds140sp = Inst::Sd(SdInst::new(REG_S1.into(), (40).into(), REG_SP.into()));
         let mvs5a0 = Inst::Mv(MvInst::new(REG_S5.into(), REG_A0.into()));
         let mvs2a2 = Inst::Mv(MvInst::new(REG_S2.into(), REG_A2.into()));
-
-        //    4   │ mv> s5,a0
-        //    3   │ mv> s2,a2
         //    2   │ sext.w> s3,a1
-        //    1   │ addi> s6,a0,4
+        let addis6a04 = Inst::Add(AddInst::new(REG_S6.into(), REG_A0.into(), (4).into()));
-        //   40   │ li> s4,1
+        let lis41 = Inst::Add(AddInst::new(REG_S4.into(), REG_ZERO.into(), (1).into()));
+        entry.extend_insts(
+            vec![
+                lia51,
+                blea1a5L20,
+                addispsp_64,
+                sds232sp,
+                sds324sp,
+                sds416sp,
+                sds58sp,
+                sds60sp,
+                sdra56sp,
+                sds048sp,
+                sds140sp,
+                mvs5a0,
+                mvs2a2,
+                addis6a04,
+                lis41
+            ]
+        );
+
+        let mut l6 = Block::new("L6".into());
+        let bles3s4L23 = Inst::Ble(BleInst::new(REG_S3.into(), REG_S4.into(), "L23".into()));
+        // addi s1 s3 -2 =
+        let addiws1s3_2 = Inst::Add(AddInst::new(REG_S1.into(), REG_S3.into(), (-2).into()));
+        let sllia5s132 = Inst::Sll(SllInst::new(REG_A5.into(), REG_S1.into(), (32).into()));
+        let srlis1a530 = Inst::Srl(SrlInst::new(REG_S1.into(), REG_A5.into(), (30).into()));
+        let mvs0s5 = Inst::Mv(MvInst::new(REG_S0.into(), REG_S5.into()));
+        let adds1s1s6 = Inst::Add(AddInst::new(REG_S1.into(), REG_S1.into(), REG_S6.into()));
     }
 }

src/ch3/FuncPoint.s

@@ -1,184 +0,0 @@
-	.file	"FuncPoint.c"
-	.option pic
-	.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0"
-	.attribute unaligned_access, 0
-	.attribute stack_align, 16
-	.text
-	.align	1
-	.globl	ascending
-	.type	ascending, @function
-ascending:
-	sgt	a0,a0,a1
-	ret
-	.size	ascending, .-ascending
-	.align	1
-	.globl	descending
-	.type	descending, @function
-descending:
-	slt	a0,a0,a1
-	ret
-	.size	descending, .-descending
-	.align	1
-	.globl	sort
-	.type	sort, @function
-sort:
-	li	a5,1
-	ble	a1,a5,.L20
-	addi	sp,sp,-64
-	sd	s2,32(sp)
-	sd	s3,24(sp)
-	sd	s4,16(sp)
-	sd	s5,8(sp)
-	sd	s6,0(sp)
-	sd	ra,56(sp)
-	sd	s0,48(sp)
-	sd	s1,40(sp)
-	mv	s5,a0
-	mv	s2,a2
-	sext.w	s3,a1
-	addi	s6,a0,4
-	li	s4,1
-.L6:
-	ble	s3,s4,.L23
-	addiw	s1,s3,-2
-	slli	a5,s1,32
-	srli	s1,a5,30
-	mv	s0,s5
-	add	s1,s1,s6
-.L8:
-	lw	a1,4(s0)
-	lw	a0,0(s0)
-	jalr	s2
-	beq	a0,zero,.L7
-	lw	a4,0(s0)
-	lw	a5,4(s0)
-	sw	a4,4(s0)
-	sw	a5,0(s0)
-.L7:
-	addi	s0,s0,4
-	bne	s0,s1,.L8
-	addiw	s3,s3,-1
-	bne	s3,s4,.L6
-	ld	ra,56(sp)
-	ld	s0,48(sp)
-	ld	s1,40(sp)
-	ld	s2,32(sp)
-	ld	s3,24(sp)
-	ld	s4,16(sp)
-	ld	s5,8(sp)
-	ld	s6,0(sp)
-	addi	sp,sp,64
-	jr	ra
-.L23:
-	addiw	s3,s3,-1
-	j	.L6
-.L20:
-	ret
-	.size	sort, .-sort
-	.section	.rodata.str1.8,"aMS",@progbits,1
-	.align	3
-.LC1:
-	.string	"%d "
-	.text
-	.align	1
-	.globl	printArray
-	.type	printArray, @function
-printArray:
-	ble	a1,zero,.L29
-	addi	sp,sp,-32
-	slli	a1,a1,2
-	sd	s0,16(sp)
-	sd	s1,8(sp)
-	sd	s2,0(sp)
-	sd	ra,24(sp)
-	mv	s0,a0
-	add	s1,a0,a1
-	lla	s2,.LC1
-.L26:
-	lw	a1,0(s0)
-	mv	a0,s2
-	addi	s0,s0,4
-	call	printf@plt
-	bne	s0,s1,.L26
-	ld	s0,16(sp)
-	la	a5,stdout
-	ld	ra,24(sp)
-	ld	s1,8(sp)
-	ld	s2,0(sp)
-	ld	a1,0(a5)
-	li	a0,10
-	addi	sp,sp,32
-	tail	putc@plt
-.L29:
-	la	a5,stdout
-	ld	a1,0(a5)
-	li	a0,10
-	tail	putc@plt
-	.size	printArray, .-printArray
-	.section	.rodata.str1.8
-	.align	3
-.LC2:
-	.string	"Original array: "
-	.align	3
-.LC3:
-	.string	"Sorted array in ascending order: "
-	.align	3
-.LC4:
-	.string	"Sorted array in descending order: "
-	.section	.text.startup,"ax",@progbits
-	.align	1
-	.globl	main
-	.type	main, @function
-main:
-	lla	a5,.LANCHOR0
-	ld	a3,0(a5)
-	ld	a4,8(a5)
-	ld	a5,16(a5)
-	addi	sp,sp,-48
-	lla	a0,.LC2
-	sd	ra,40(sp)
-	sd	a3,8(sp)
-	sd	a4,16(sp)
-	sd	a5,24(sp)
-	sd	s0,32(sp)
-	addi	s0,sp,8
-	call	puts@plt
-	mv	a0,s0
-	li	a1,6
-	call	printArray
-	lla	a2,ascending
-	li	a1,6
-	mv	a0,s0
-	call	sort
-	lla	a0,.LC3
-	call	puts@plt
-	mv	a0,s0
-	li	a1,6
-	call	printArray
-	lla	a2,descending
-	li	a1,6
-	mv	a0,s0
-	call	sort
-	lla	a0,.LC4
-	call	puts@plt
-	mv	a0,s0
-	li	a1,6
-	call	printArray
-	ld	ra,40(sp)
-	ld	s0,32(sp)
-	li	a0,0
-	addi	sp,sp,48
-	jr	ra
-	.size	main, .-main
-	.section	.rodata
-	.align	3
-	.set	.LANCHOR0,. + 0
-.LC0:
-	.word	5
-	.word	2
-	.word	9
-	.word	1
-	.word	5
-	.word	6
-	.ident	"GCC: (Debian 12.2.0-13) 12.2.0"
-	.section	.note.GNU-stack,"",@progbits

src/ch4/mod.rs

@@ -0,0 +1,5 @@
+mod var_def2;
+mod var_def3;
+
+pub use var_def2::*;
+pub use var_def3::*;

src/ch4/var_def2.rs

@@ -0,0 +1,34 @@
+mod tests {
+    use std::ops::Add;
+
+    use compiler::backend::*;
+    use var::{ PrimVar, Var };
+
+    #[test]
+    pub fn var_def2() {
+        // main:
+        let mut entry = Block::new("entry".into());
+        let laa0b = Inst::La(LaInst::new(REG_A0.into(), "b".into()));
+        let addiwa0a05 = Inst::Add(AddInst::new(REG_A0.into(), REG_A0.into(), (5).into()));
+        let ret = Inst::Ret;
+        entry.extend_insts(vec![laa0b, addiwa0a05, ret]);
+        let b = Var::Prim(
+            PrimVar::IntVar(var::IntVar {
+                name: "b".into(),
+                init: (5).into(),
+                is_const: true,
+            })
+        );
+
+        let Main = Func::new("main".into(), Vec::new(), entry);
+        let m_def02 = Module {
+            name: "var_def02".into(),
+            global: Vec::new(),
+            funcs: vec![Main],
+            entry: Some("main".into()),
+        };
+
+        let asm = m_def02.gen_asm();
+        print!("{}", asm);
+    }
+}

src/ch4/var_def3.rs

@@ -0,0 +1,22 @@
+mod tests {
+    use compiler::backend::*;
+
+    #[test]
+    pub fn var_def3() {
+        let mut entry = Block::new("entry".into());
+        let lia05 = Inst::Add(AddInst::new(REG_A0.into(), REG_ZERO.into(), (5).into()));
+        let ret = Inst::Ret;
+        entry.extend_insts(vec![lia05, ret]);
+
+        let Main = Func::new("main".into(), Vec::new(), entry);
+        let m_def02 = Module {
+            name: "var_def02".into(),
+            global: Vec::new(),
+            funcs: vec![Main],
+            entry: Some("main".into()),
+        };
+
+        let asm = m_def02.gen_asm();
+        print!("{}", asm);
+    }
+}

src/main.rs

@@ -1,6 +1,8 @@
 mod ch2;
 mod ch3;
 
+mod ch4;
+
 use std::{fs::File, io::Write};
 
 use compiler::backend::*;